參數(shù)資料
型號(hào): LC75754M
廠商: Sanyo Electric Co.,Ltd.
英文描述: 1/3 Duty VFD Driver(1/3占空VFD顯示驅(qū)動(dòng)器)
中文描述: 1 / 3職務(wù)VFD驅(qū)動(dòng)器(1 / 3占空變頻顯示驅(qū)動(dòng)器)
文件頁數(shù): 5/10頁
文件大?。?/td> 153K
代理商: LC75754M
No. 5950-5/10
LC75754M
CCB address : Transfer 11000001B(83
H
) as shown in Figure 2
DM0 to DM9 : Dimmer data
This data controls the duty of the G1 to G3 digit output pins, and consists of 10 bits with DM0 being
the LSB. Note that the intensity of the display can be adjusted by controlling the duty of the G1 to G3
digit output pins.
The relationship between the dimmer data and the dimmer value is as follows.
D1 to D24 : Display data for the G1 digit output pin.
Dn (n = 1 to 24) = 1 : On
Dn (n = 1 to 24) = 0 : Off
D25 to D48 : Display data for the G2 digit output pin.
Dn (n = 25 to 48) = 1 : On
Dn (n = 25 to 48) = 0 : Off
D49 to D72 : Display data for the G3 digit output pin.
Dn (n = 49 to 72) = 1 : On
Dn (n = 49 to 72) = 0 : Off
t3, t4 : See Figure 4.
DM9
DM8
DM7
DM6
DM5
DM4
DM3
DM2
DM1
DM0
Dimmer value (t4/t3)
0
0
0
0
0
0
0
0
0
0
0/1024
0
0
0
0
0
0
0
0
0
1
1/1024
0
0
0
0
0
0
0
0
1
0
2/1024
1
1
1
1
1
1
1
1
0
0
1020/1024
1
1
1
1
1
1
1
1
0
1
1021/1024
1
1
1
1
1
1
1
1
1
0
1022/1024
1
1
1
1
1
1
1
1
1
1
Not used
Correspondence between Display Data (D1 to D72) and Segment Output Pins
Example : Segment output pin S11 is controlled as follows :
Segment output pins
G1
G2
G3
S1
D1
D25
D49
S2
D2
D26
D50
S3
D3
D27
D51
S4
D4
D28
D52
S5
D5
D29
D53
S6
D6
D30
D54
S7
D7
D31
D55
S8
D8
D32
D56
S9
D9
D33
D57
S10
D10
D34
D58
S11
D11
D35
D59
S12
D12
D36
D60
Segment output pins
G1
G2
G3
S13
D13
D37
D61
S14
D14
D38
D62
S15
D15
D39
D63
S16
D16
D40
D64
S17
D17
D41
D65
S18
D18
D42
D66
S19
D19
D43
D67
S20
D20
D44
D68
S21
D21
D45
D69
S22
D22
D46
D70
S23
D23
D47
D71
S24
D24
D48
D72
Display data
Segment output pin S11 state
D11
D35
D59
0
0
0
The segments corresponding to the G1, G2, and G3 digit output pins are off
0
0
1
The segments corresponding to the G3 digit output pin are on
0
1
0
The segments corresponding to the G2 digit output pin are on
0
1
1
The segments corresponding to the G2 and G3 digit output pins are on
1
0
0
The segments corresponding to the G1 digit output pin are on
1
0
1
The segments corresponding to the G1 and G3 digit output pins are on
1
1
0
The segments corresponding to the G1 and G2 digit output pins are on
1
1
1
The segments corresponding to the G1, G2, and G3 digit output pins are on
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