參數(shù)資料
型號： LC75411WS
文件頁數(shù)： 9/33頁
文件大?。?/td> 669K
代理商： LC75411WS
No. 6928-9/33
LC75411ES, 75411WS
Parameter
Symbol
Pin Name
Conditions
Ratings
Unit
min
typ
max
[Fader Block]
Input resistance
Rfed
LFIN, RFIN
25
50
100
k
dB
0dB to –2dB
±0.5
Step setting error
ATerr
–2dB to –20dB
±1
dB
–20dB to –30dB
±2
dB
–30dB to –60dB
±3
dB
L/R balance
BAL
±0.5
dB
[General]
Total harmonic distortion
THD (1)
V
IN
= –10dBV, f = 1 kHz
V
IN
= –10dBV, f = 10 kHz
V
IN
= 1Vrms, f = 1 kHz
V
IN
= 1Vrms, f = 1 kHz
Vomin (1) V
IN
= 1Vrms, f = 1 kHz
V
IN
= 1Vrms, f = 1 kHz
INMUTE, fader –
∞
V
N
(1)
Flat overall, IHF-A filter
V
N
(2)
Flat overall, 20 to 20 kHzBPF
I
DD
I
IH
CL, DI, CE, V
IN
= 9 V
I
IL
CL, DI, CE, V
IN
= 0 V
THD = 1%, R
L
= 10 k
flat overall, f
IN
= 1 kHz
0.004
0.01
%
THD (2)
0.006
0.01
%
Input crosstalk
CT
80
88
dB
L/R crosstalk
CT
80
88
dB
Maximum attenuated output
80
88
dB
Vomin (2)
90
95
dB
Output noise voltage
5
10
μV
7
15
μV
Current drain
33
40
mA
Input high-level current
10
μA
Input low-level current
–10
μA
Maximum input voltage
V
CL
2.5
2.9
Vrms
Continued from preceding page.
Control Timing and Data Format
To control the LC75411ES and LC75411WS input specified serial data to the CE, CL, and DI pins.
The data configuration consists of a total of 52 bits broken down into 8 address bits and 44 data bits.
CE
DI
CL
D43
D42
D41
D40
D39
D38
D5
D4
D3
D2
D0
D1
A3
A2
A1
A0
B3
B2
B1
B0
1
μ
s
min
1
μ
s
min
1
μ
s min
≤
T
DEST
1
μ
s
min
1
μ
s
min
1
μ
s
min
CE
DI
CL
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