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參數(shù)資料
| 型號(hào)： | LC75010W |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 16-bit fixed point DSP with Flash |
| 中文描述： | 具有閃存的 16 位定點(diǎn) DSP |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 128K |
| 代理商： | LC75010W |
No. N7349-9/12
LC75010W
t
CL
t
EH
t
ES
t
HD
t
SU
Old
New
t
LC
t
DH
t
DC
t
DC
t
EL
t
CH
≈
When CL is stopped at the low level
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
V
IH
VIH
V
IL
V
IL
V
IL
DO
CL
DI
CE
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
t
CL
t
EH
t
ES
t
HD
t
SU
Old
New
t
LC
t
DH
t
DC
t
EL
t
CH
≈
When CL is stopped at the high level
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
V
IL
V
IL
V
IH
DO
Internal
data latch
CL
DI
CE
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
≈
Internal
data latch
Serial Data Timing
CL: Normally high
CL: Normally low
Reset Timing
After power has been applied, and after crystal oscillator operation and PLL circuit operation have stabilized, a reset must
be applied at the point that the Vref voltages (Vref1, Vref2, and Vref3) exceed the minimum level of 2.35 V. The reset
period must be set up to include a period of at least 0.5 μs during which the reset signal is held fixed at the low level.
Audio processing (audio input/audio output) cannot be performed during the A/D converter calibration period (100 ms),
which directly follows the reset.
Note on Changes to the DSP Core Main Clock
The LC75010W DSP core main clock can be switched by setting the TEST8 pin either low or high as shown below.
TEST8
DSP core main clock (Crystal oscillator: 16.9344 MHz)
Low (DV
SS
)
High (
DV
DD
3.3
)
38.1024 MHz
40.2192 MHz
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