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參數(shù)資料
| 型號： | LC74785 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | On-Screen Display Controller LSI(屏幕顯示控制器規(guī)模集成電路（LSI）) |
| 中文描述： | 屏幕顯示控制器芯片（屏幕顯示控制器規(guī)模集成電路（LSI）的） |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 268K |
| 代理商： | LC74785 |
No. 5520-3/24
LC74785, LC74785M
Pin No.
Pin
Function
Notes
15
CV
IN
V
DD
1
SYN
IN
CDLR
Video signal input
Composite video signal input
16
Power supply
Power supply (+5 V: digital system power supply)
17
Sync separator circuit input
Video signal input for the built-in sync separator circuit
18
Background color phase adjustment
Background color phase adjustment. Connect to ground through a resistor and a capacitor.
19
SEP
OUT
Composite synchronizing signal output
20
SEP
IN
21
CS2
Enable input
22
CPDT
Data output
23
RST
Reset input
24
V
DD
1
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
Video signal output for the built-in sync separator circuit. Can be switched to function
as an output for signal (high or ST. pulse) due to MOD0 by setting SEL0 high.
Inputs the vertical synchronizing signal created by integrating the SEP
OUT
pin output
signal.
An integration circuit must be connected to the SEP
OUT
pin. This pin must be tied to
V
DD
1 if unused. This pin can be switched to function as the frame signal input mode
by setting SEL1 high. (This is valid when CTL3 is set to 1.)
Vertical synchronizing signal input
EDS data output enable input. EDS data output is enabled when this pin is low. A
pull-up resistor is built in. (The input has hysteresis characteristics.)
EDS data output (This pin can be either an n-channel open-drain output or a CMOS
output.)
System reset input
A pull-up resistor is built in. (The input has hysteresis characteristics.)
Continued from preceding page.
Note: Both V
DD
1 pins must be connected to the power supply.
Note: When the Xtal
IN
pin is used in clock input mode, extreme care must be taken to prevent noise from entering the input signal.
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
V
DD
V
IN
V
OUT
Pd max
V
DD
1 and V
DD
2
All input pins
V
SS
–0.3 to V
SS
+7.0
V
SS
–0.3 to V
DD
+0.3
V
SS
–0.3 to V
DD
+0.3
V
Input voltage
V
Output voltage
LN21, CPDT, SEP
OUT
, and SYNC
JDG
Ta = 25°C
V
Allowable power dissipation
350
mW
Operating temperature
Topr
–30 to +70
°C
Storage temperature
Tstg
–40 to +125
°C
Specifications
Absolute Maximum Ratings
at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
DD
1
V
DD
2
V
DD
1
V
DD
2
RST, CS1, CS2, SIN, SCLK, SEP
IN
,
and MUTE
4.5
5.0
5.5
V
4.5
5.0
1.27V
DD
1
V
V
IH
1
0.8V
DD
1
V
DD
1 + 0.3
V
Input high-level voltage
V
IH
2
CTRL1
0.7V
DD
1
V
DD
1 + 0.3
V
V
IL
1
RST, CS1, CS2, SIN, SCLK, SEP
IN
,
and MUTE
V
SS
– 0.3
0.2V
DD
1
V
Input low-level voltage
V
IL
2
CTRL1
V
SS
– 0.3
0.3V
DD
1
V
Pull-up resistance
R
PU
Applies to pins set for the RST, CS1, CS2,
SIN, SCLK, and MUTE pin options.
25
50
90
k
Composite video signal input voltage
V
IN
1
V
IN
2
CV
IN
; V
DD
1 = 5 V
SYN
IN
; V
DD
1 = 5 V
Xtal
IN
(When external clock input is used)
f
in
= 2 fsc or 4 fsc ; V
DD
1 = 5 V
The Xtal
IN
and Xtal
OUT
oscillator pins
(2 fsc: NTSC)
2.0
Vp-p
1.5
2.0
2.5
Vp-p
Input voltage
V
IN
3
0.10
5.0
Vp-p
F
OSC
1
7.159
MHz
Oscillator frequency
F
OSC
1
The Xtal
IN
and Xtal
OUT
oscillator pins
(4 fsc: NTSC)
14.318
MHz
F
OSC
2
The OSC
IN
and OSC
OUT
oscillator pins
(LC oscillator)
5
10
MHz
Allowable Operating Ranges
at Ta = –30 to +70°C
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