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參數(shù)資料
| 型號(hào)： | LC74725M |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | On-Screen Display Controller LSI |
| 中文描述： | 屏幕顯示控制器芯片 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 260K |
| 代理商： | LC74725M |
No. 5213-2/16
LC74725, 74725M
Pin Assignment
Pin Functions
Note: Both V
DD
1 pins must be connected to the power supply.
Pin No.
Symbol
Function
Description
1
V
SS
1
Ground
Ground connection (digital system ground)
2
Xtal
IN
Connections for the external crystal and capacitors used to form a crystal oscillator for internal
synchronizing signal generation. Alternatively, these pins can be used for external clock input
(2fsc or 4fsc).
Crystal oscillator
3
Xtal
OUT
4
CTRL1
Crystal oscillator input
switching
Switches between external clock input mode and crystal oscillator mode. Low: crystal oscillator
mode, high: external clock input mode.
5
LN21
Data output
Line 21H pulse output (MOD0 = low: even field, MOD0 = high: both fields output)
6
OSC
IN
OSC
OUT
LC oscillator
Connections for the external coil and capacitor used to form the character output dot clock
generation oscillator.
7
Outputs the judgment as to where there are or are not external synchronizing signals present.
Outputs a high level when there are synchronizing signals.
SEL0 = high: Outputs field discrimination pulses (O/E pulses)
Outputs the dot clock (LC oscillator) when the CS1 pin is high and the RST pin is low. A
command is provided that turns this output off.
Outputs the crystal oscillator clock when the CS1 pin is low and the RST pin is low. A
command is provided that turns this output off.
External synchronizing
signal judgment output
8
SYNC
JDG
9
CS1
Enable input
Enable input for OSD serial data input. Serial data input is enabled when this pin is low. A pull-
up resistor is built in (hysteresis input).
10
SCLK
Clock input
Serial data input clock input.
A pull-up resistor is built in (hysteresis input).
11
SIN
Data input
Serial data input. A pull-up resistor is built in (hysteresis input).
12
V
DD
2
CV
OUT
NC
Power supply
Composite video signal level adjustment power supply (analog system power supply)
13
Video signal output
Composite video signal output pin
14
Must be either connected to ground or left open.
15
CV
IN
V
DD
1
SYN
IN
V
SS
1
Video signal input
Composite video signal input pin
16
Power supply
Power supply (+5 V: digital system power supply)
17
Sync separator circuit input
Video signal input to the built-in sync separator circuit
18
Ground
Ground (digital system ground)
19
SEP
OUT
Composite synchronizing
signal output
Video signal output from the built-in sync separator circuit
Vertical synchronizing
signal input
Inputs the vertical synchronizing signal generated by integrating the SEP
OUT
pin output signal.
An integrating circuit must be inserted between the SEP
OUT
pin and this pin. This pin must be
tied to V
DD
1 if unused.
Enable input for EDS data output. EDS data output is enabled when this input is low. A pull-up
resistor is built in (hysteresis input).
20
SEP
IN
21
CS2
Enable input
22
CPDT
Data output
EDS data output (either an n-channel open-drain or a CMOS output circuit)
23
RST
Reset input
System reset input. A pull-up resistor is built in (hysteresis input).
24
V
DD
1
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
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