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參數(shù)資料
| 型號： | LC73101C |
| 文件頁數(shù)： | 8/34頁 |
| 文件大?。?/td> | 217K |
| 代理商： | LC73101C |
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Display Data RAM
Display data RAM
The display data RAM holds the dot data to be displayed, and has an 80 (10-page
×
8-bit)
×
132-bit organization. This
memory is accessed by specifying a page address and a column address to access data in 8-bit units. Since the display
data D7 to D0 from the microcontroller corresponds to the direction of the LCD common pins as shown in figure 3,
when two LC73101C chips are used together, there are few constraints or limitations when transferring data, and
highly flexible display structures can be implemented easily. Read and write operations to this display data RAM are
performed through an I/O buffer, and thus these operations are independent of signal reads for LCD drive. This means
that flicker and other problems do not occur when the display RAM is accessed asynchronously during display on the
LCD panel.
Figure 3 Noninverting LCD Display
Page address circuit
The display data RAM page address shown in figure 4 is specified using the Page Address Set command. The page
address must be specified again to access a different page.
Column address circuit
The display data RAM column address shown in figure 4 is specified using the Column Address Set command. Since
the specified column address is incremented each time a display data read or write command is input, the
microcontroller can access the display data consecutively. Note that this column address incrementing stops when the
column address reaches 83H. Since the column address and the page address are mutually independent, the column
address and the page address must both be specified again to access a different column on a different page.
Additionally, the correspondence between the display data RAM column address and segment output can be inverted
with the CSS command (Column Address/Segment Output Correspondence Selection command) as shown in table 3.
This reduces constraints on IC positioning when assembling LCD modules.
No. 6853-8/34
LC73101C
D0
D1
D2
D3
D4
0
1
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
0
1
0
1
0
COM0
COM1
COM2
COM3
COM4
Display data RAM
LCD display
Table 3
CSS setting (D0)
Column address
Segment output
0
0H
→
→
→
→
SEG0
83H
SEG131
1
0H
SEG131
83H
SEG0
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