
SYNC_RST
0: (default)
1: Resets just the synchronization regeneration circuit.
Clears the synchronization status and the synchronization protection status in the synchronization circuit block, and
sets the circuit to the unsynchronized state. This allows the circuit to quickly pull in to frame synchronization when
the frame synchronization is incorrect for the new reception data following tuning, when the radio has been tuned to
a new station. While this flag is used for synchronization related section of the system, it does not initialize the
registers that set the number of allowable BIC errors, the block synchronization forward and back protection counts,
and the frame synchronization forward and back protection counts. Also note that during a synchronization block
reset, the INT signal is not output and the DO pin outputs a high level (high-impedance).
This flag is not automatically reset to 0. Applications must send a 0 value after setting this flag.
INT_MOVE
0: Data is only output when error correction has completed, layer 2 CRC has completed, and the data was received with
the circuit synchronized. (default)
1: All data is output. (Operation is identical to that of the LC72700E.)
In the default state, this IC only outputs data that has been fully error corrected and that was received in both block
and frame synchronization. (This also includes the layer 2 CRC check.)
To acquire all data as provided by the LC72700, applications must set both this flag and the VEC_OUT (BIT2) flag
in control register 2 as described below.
DO_MOVE (Valid only when SP is high.)
0: The high state (high impedance) is held at all times other than when data is being output. (default)
1: Operate identically to the LC72700 when changes are linked to the INT signal, i.e. when both INT_MOVE and
VEC_OUT are set to 1.
CRC4_RST
0: (default)
1:Reset the layer 4 CRC detection circuit.
This flag is not automatically reset to 0. Applications must send a 0 value after setting this flag.
No. 6167-13/29
LC72711W, 72711LW
Control Register 2
Address
Register
R/W
Initial value
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
05H
CTL2
W
00H
SUBBLK
BLK_RST
DACK
DREQ
RDY
VEC_OUT
DMA_RD
DMA
DMA (Valid only when SP is low.)
0: Do not use DMA transfer for readout of post-error correction data. (default)
1: Use DMA transfer for readout of post-error correction data.
DMA_RD (Valid only when SP is low.)
0: Use the RD signal as the DMA transfer read control signal. (default)
1: Use the DACK signal as the DMA transfer read control signal.
VEC_OUT
0: Do not perform post-vertical correction output when vertical correction processing is not performed. (default)
1: Output all data, even when vertical correction processing is not performed. (Operation identical to that of the
LC72700E)
When this flag is set and a frame of data with absolutely no errors is received, data that is completely identical to the
corresponding post-horizontal correction data is output with the timing of the output of post-vertical correction data,
even if vertical correction is not performed.
This flag must be set to create interface specifications identical to those of the LC72700.
RDY (Valid only when SP is low.)
0: The RDY output is issued with timing 1. (default)
1: The RDY output is issued with timing 2.
DREQ (Valid only when SP is low.)
0: Negative logic is used for the polarity of the DREQ signal. (default)
1: Positive logic is used for the polarity of the DREQ signal.
DACK (Valid only when SP is low.)
0: Negative logic is used for the polarity of the DACK signal. (default)
1: Positive logic is used for the polarity of the DACK signal.