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參數(shù)資料
| 型號(hào)： | LC7265 |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP42 |
| 封裝： | SDIP-42 |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大?。?/td> | 127K |
| 代理商： | LC7265 |
2-4 . FIF1, FIF2, FIF3 : FM IF select pins
FIF1
00001111
FIF2
00110011
FIF3
01010101
IF (MHz)
+10.700
+10.725
+10.675
+10.750
–10.700
–10.725
–10.675
–10.650
2-5 . AIF1, AIF2 : AM IF select pins
AIF1
0011
AIF2
0101
IF (kHz)
+450 (2)
+450 (1)
+455
+469
(Note) 450 kHz(1) : 10 kHz step display, others : 1 kHz step display
1 : High level (VDD)
0 : Low level (VSS)
2-6 . HLD : Display contents hold pin
Normally, this pin is set at high level. To hold display contents, this pin is set at low level. Connecting time constant circuit
to this pin makes it possible to hold display contents for a certain period of time at the time of FM/MW, LW band
selection.
2-7 . BLK : Display blanking pin
2-8 . FMI, AMI : Local oscillation signal input pins
FMI — For FM
: 0.7Vp-p input sensitivity
AMI — For MW, LW : 1.0Vp-p input sensitivity (VDD =8to10 V,fIN = 0.5 to 0.9 MHz)
0.5Vp-p input sensitivity (other than above)
2-9 . A/F : FM/MW, LW select pin
FM
— Pin open or high level
MW, LW — Low level
2-10 . 50 Hz : 50 Hz time base output pin
Internal clock
Depending on C, R
Display contents hold
Threshold
voltage of
e
HLD
A/F
Example of blanking misdisplay
at the time of application of power.
LC7265
No.1197-4/6
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