參數(shù)資料
型號(hào)： LC723740
廠(chǎng)商： Sanyo Electric Co.,Ltd.
英文描述： ETR Microcontrollers(大容量電子調(diào)諧應(yīng)用的微控制器)
中文描述： 東突微控制器（大容量電子調(diào)諧應(yīng)用的微控制器）
文件頁(yè)數(shù)： 13/14頁(yè)
文件大?。?/td> 229K
代理商： LC723740
No. 5931-13/14
LC723732/40/48/56/64
Continued from preceding page.
Mnemonic
Operand
Function
Operations function
Instruction format
1st
2nd
AND
r
M
AND M with r
r
←
(r) AND (M)
M
←
(M) AND I
r
←
(r) OR (M)
M
←
(M) OR I
r
←
(r) XOR (M)
M
←
(M) XOR I
0 0 1 0 0 0 DH
DL
r
ANDI
M
I
AND I with M
0 0 1 0 0 1 DH
DL
I
OR
r
M
OR M with r
0 0 1 0 1 0 DH
DL
r
ORI
M
I
OR I with M
0 0 1 0 1 1 DH
DL
I
EXL
r
M
Exclusive OR M with r
0 0 1 1 0 0 DH
DL
r
EXLI
M
I
Exclusive OR M with M
0 0 1 1 0 1 DH
DL
I
SHMR
M
Shift M right with carry
1 1 1 1 1 1 1 1 1 0 DH
DL
LD
r
M
Load M to r
r
←
(M)
M
←
(r)
r
←
(M
ADR
)
M
ADR
←
(r)
1 1 0 1 0 0 DH
DL
r
ST
M
r
Strore r to M
1 1 0 1 0 1 DH
DL
r
LDA
r
Load M specified by ADR to r
1 1 1 1 1 0 0 1 1 1 0 0
r
STA
r
Store r to M specified by ADR
1 1 1 1 1 0 0 1 1 1 0 1
r
MVRD
r
M
Move M to destination M referring to r in
the same row
[DH, rn]
←
(M)
1 1 0 1 1 0 DH
DL
r
MVRS
M
r
Move source M referring to r to M in the
same row
M
←
(DH, rn)
1 1 0 1 1 1 DH
DL
r
MVSR
M1
M2
Move M to M in the same row
[DH, DL1]
←
[DH, DL2]
M
←
I
1 1 1 0 0 0 DH
DL
DL2
MVI
M
I
Move I to M
1 1 1 0 0 1 DH
DL
I
TMT
M
N
Test M bits, then skip if all bits specified
are true
if M(N) = all 1, then skip
1 1 1 1 0 0 DH
DL
N
TMF
M
N
Test M bits, then skip if all bits specified
are false
if M(N) = all 0, then skip
1 1 1 1 0 1 DH
DL
N
JMP
ADDR
Jump to the address
PC
←
ADDR
PC
←
(ADR)
PC
←
(PC) + 1 + ADDR
PC
←
ADDR
Stack
←
(PC) + 1
PC
←
(ADR)
Stack
←
(PC) + 1
PC
←
Stack
PC
←
Stack + 1
PC
←
Stack,
BANK
←
Stack
PC
←
Stack + 1,
BANK
←
Stack
PC
←
Stack,
BANK
←
Stack,
CARRY
←
Stack
PAGE
←
Stack
1 0
ADDR(14 bits)
JMPA
Jump to the address specified by ADR
0 0 0 0 0 0 0 0 1 1 1 0
JMPR
ADDR
Jump to the relative address
1 1 1 1 1 0 1 0
ADDR (8 bits)
CAL
ADDR
Call subroutine
1 1 0 0
ADDR(12 bits)
CALA
Call subroutine specified by ADR
0 0 0 0 0 0 0 0 1 1 1 1
RT
Return from subroutine
0 0 0 0 0 0 0 0 1 0 0 0
RTS
Return from subroutine and skip
0 0 0 0 0 0 0 0 1 0 1 0
RTB
Return from subroutine with BANK data
1 1 1 1 1 1 1 1 1 1 0 0
RTBS
Return from subroutine with BANK data
and skip
1 1 1 1 1 1 1 1 1 1 0 1
RTI
Return from interrupt
0 0 0 0 0 0 0 0 1 0 0 1
SS
SWR
N
Set status register
(Status W-reg)N
←
1
1 1 1 1 1 1 1 1 0 0 SWR
N
RS
SWR
N
Reset status register
(Status W-reg)N
←
0
1 1 1 1 1 1 1 1 0 1 SWR
N
TST
SRR
N
Test status register true
if (Status R-reg)N = all1, then skip
1 1 1 1 1 0 0 0 0
SRR
N
TSF
SRR
N
Test status register false
if (Status R-reg)N = all0, then skip
1 1 1 1 1 0 0 0 1
SRR
N
PLL
M
Load M to PLL register
PLL reg
←
PLL data
1 1 1 1 1 0 0 1 0 1 DH
DL
PUT
PEn
Put data of DTR to perifheral register
PEn
←
(DTR)
1 1 1 1 1 0 0 1 1 0 1 0
PEn
GET
PEn
Get peripheral data to DTR
DTR
←
(PEn)
1 1 1 1 1 0 0 1 1 0 1 1
PEn
SIO
I1
I2
Serial I/O control
SIO reg
←
I1, I2
UCCW1
←
I
UCCW2
←
I
BEEP reg
←
I
DZC reg
←
I
Timer reg
←
I
IOS1 reg PW1n
←
N
IOS2 reg PW2n
←
N
0 0 0 0 0 0 0 1
I1
I2
UCS
I
Set I to UCCW1
0 0 0 0 0 0 0 0 0 0 0 1
I
UCC
I
Set I to UCCW2
0 0 0 0 0 0 0 0 0 0 1 0
I
BEEP
I
Beep control
0 0 0 0 0 0 0 0 0 1 1 0
I
DZC
I
Dead zone control
0 0 0 0 0 0 0 0 1 0 1 1
I
TMS
I
Set timer register
0 0 0 0 0 0 0 0 1 1 0 0
I
IOS1
PW1n
N
Set port control word1
1 1 1 1 1 1 1 0
PW1n
N
IOS2
PW2n
N
Set port control word2
1 1 1 1 1 0 1 1
PW2n
N
L
i
T
B
i
J
I
t
H
S
i
I
g
f e d c b a 9 8 7 6 5 4 3 2 1 0
carry
(M)
Continued on next page.
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