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參數(shù)資料
| 型號： | LC72349W |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Low-Voltage ETR Controller with On-Chip LCD Driver |
| 中文描述： | 低電壓東突控制器的片上LCD驅(qū)動器 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 119K |
| 代理商： | LC72349W |
LC72340 Series Instruction Set
Terminology
ADDR
b
C
DH
DL
I
M
N
Rn
Pn
PW
r
( ), [ ]
M (DH, DL) : Data memory specified by DH, DL
: Program memory address
: Borrow
: Carry
: Data memory address High (Row address) [2 bits]
: Data memory address Low (Column address) [4 bits]
: Immediate data [4 bits]
: Data memory address
: Bit position [4 bits]
: Resister number [4 bits]
: Port number [4 bits]
: Port control word number [4 bits]
: General register (One of the addresses from 00H to 0FH of BANK0)
: Contents of register or memory
No. 6472-11/14
LC72348G/W, 72349G/W
Mnemonic
Operand
Function
Operations function
Instruction format
1st
2nd
AD
r
M
Add M to r
r
←
(r) + (M)
r
←
(r) + (M), skip if carry
r
←
(r) + (M) + C
r
←
(r) + (M) + C
skip if carry
M
←
(M) + I
M
←
(M) + I, skip if carry
M
←
(M) + I + C
M
←
(M) + I + C,
skip if carry
r
←
(r) – (M)
r
←
(r) – (M),
skip if borrow
r
←
(r) – (M) – b
r
←
(r) – (M) – b,
skip if borrow
M
←
(M) – I
M
←
(M) – I,
skip if borrow
M
←
(M) – I – b
M
←
(M) – I – b,
skip if borrow
ADS
r
M
Add M to r, then skip if carry
AC
r
M
Add M to r with carry
ACS
r
M
Add M to r with carry,
then skip if carry
AI
M
I
Add I to M
AIS
M
I
Add I to M, then skip if carry
AIC
M
I
Add I to M with carry
AICS
M
I
Add I to M with carry,
then skip if carry
SU
r
M
Subtract M from r
SUS
r
M
Subtract M from r,
then skip if borrow
SB
r
M
Subtract M from r with borrow
SBS
r
M
Subtract M from r with borrow,
then skip if borrow
SI
M
I
Subtract I from M
SIS
M
I
Subtract I from M,
then skip if borrow
SIB
M
I
Subtract I from M with borrow
SIBS
M
I
Subtract I from M with borrow,
then skip if borrow
f
e
d
c
b
a
9
8
7
6
5
4
3
2
1
0
0
1
0
0
0
0
DH
DL
r
0
1
0
0
0
1
DH
DL
r
0
1
0
0
1
0
DH
DL
r
0
1
0
0
1
1
DH
DL
r
0
1
0
1
0
0
DH
DL
I
0
1
0
1
0
1
DH
DL
I
0
1
0
1
1
0
DH
DL
I
0
1
0
1
1
1
DH
DL
I
0
1
1
0
0
0
DH
DL
r
0
1
1
0
0
1
DH
DL
r
0
1
1
0
1
0
DH
DL
r
0
1
1
0
1
1
DH
DL
r
0
1
1
1
0
0
DH
DL
I
0
1
1
1
0
1
DH
DL
I
0
1
1
1
1
0
DH
DL
I
0
1
1
1
1
1
DH
DL
I
Instruc-
tions
Continued on next page.
A
S
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