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參數(shù)資料
| 型號(hào)： | LC72311W |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 128K |
| 代理商： | LC72311W |
Block Diagram
No. 6650-6/12
LC72314W, 72315W, 72316W
PHASE
DETECTOR
REFERENCE DIVIDER
DIVIDER
SYSTEM CLOCK
GENERATOR
PROGRAMMBLE DIVIDER
1/16,1/17
SEG
LA
P-ON
RESET
1/2
BANK
ADDRESS
DECODER
DATA BUS
TIMER 0
JUDGE
ALU
CF
SKIP
BANK
A
STACK
4
14
14
ADDRESS COUNTER
ADDRESS DECODER
ROM
4k
×
16bits
(LC72314)
6K
×
16bits
(LC72315)
8K
×
16bits
(LC72316)
BUS
CONTROL
JMP
CAL
RETURN
INTERRUPT
RESET
INSTRUCTION
DECODER
PLL DATA LATCH
PLL CONTROL
DATA
LATCH
/
BUS
DRIVER
DATA
LATCH
/
BUS
DRIVER
DATA
LATCH
/
BUS
DRIVER
DATA
LATCH
/
BUS
DRIVER
DATA
LATCH
/
BUS
DRIVER
BUS
DRIVER
XIN
XOUT
FMIN
PC2
PC3
PC1
PC0
PA3
PA2
PA1
PA0
TEST2
TEST1
RES
*
AMIN
S16/PH3
S15/PH2
S13/PH0
S14/PH1
LCD
PORT
DRIVER
LCPA/B
LCDA/B
EO
S12
S1
VSS
PB2
PB3
PB1
PB0
PD2
PD3
INT1/PD1
INT0/PD0
LATCH
B
LATCH
PE0/BEEP
COM1
COM2
COM3
COM4
S20/PG3
S19/PG2
S17/PG0
S18/PG1
DATA
LATCH
/
BUS
DRIVER
MPX
(6bits)
MPX
MPX
BEEP TONE
COMMON
DRIVER
DATA
LATCH
/
BUS
DRIVER
DATA
LATCH
/
BUS
DRIVER
DATA
LATCH
/
BUS
DRIVER
7
PF3/ADI3
PF1/ADI1
PF2
PF0/ADI0
PE1
VDC3
VADJ
VDD
VDC1
PL2
PL3
PL1
PL0
SIO
VDDRAM
SO1/PK2
SI1/PK3
SCK1/PK1
PK0
S24/PI3
S23/PI2
S21/PI0
S22/PI1
DATA
LATCH
/
BUS
DRIVER
S28/PJ3
S27/PJ2
S25/PJ0
S26/PJ1
DATA
LATCH
/
BUS
DRIVER
PE2
PE3
1/2
HCTR
TIME BASE
COUNTROL
UNIVERSAL
COUNTER(20bits)
COUNT END
112
1/2
1/2
1/2
RAM
256
×
4bits
(LC72314)
512
×
4bits
(LC72315/316)
1/8
Clock control
*
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC72312W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| LC72313W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| LC72314W | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Ultralow-Voltage ETR Controller with On-Chip LCD Driver |
| LC72315W | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Ultralow-Voltage ETR Controller with On-Chip LCD Driver |
| LC72316W | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Ultralow-Voltage ETR Controller with On-Chip LCD Driver |
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