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參數(shù)資料
| 型號： | LC7219M |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 160 MHz, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 212K |
| 代理商： | LC7219M |
LC7219, 7219M
No.3661–7/12
Serial Bus Data Transfer
The LC7219 and LC7219M can both transfer data in
three different modes-36-bit input data transfer, 24-bit
input data transfer and 28-bit output data transfer. The
transfer mode is selected by the four data bits on DI
immediately prior to CE going HIGH as shown in figure
6 and table 4. These bits are synchronized to the clock
and are latched into the mode register on the rising edge
of CE.
Note
× = don’t care
Programmable Divider
The configurration of the programmable divider is shown in figure 7. Input mode selection is shown in table 5.
Figure 6. Transfer mode select
Table 4. Mode selection
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Figure 7. Programmable divider
Table 5. Programmable divider selection
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Note
× = don’t care
When an FM signal is input on FMIN, the actual divider
ratio is double the set ratio. For channel steps of 1, 5 and
9 kHz, a 3.6MHz crystal should be used. The program-
mable divider ratio is determined by the setting of the DV
and SP bits as shown in table 6.
Table 6. Divider ratio settings
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Note
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