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參數(shù)資料
| 型號： | LC72146 |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDIP24 |
| 封裝： | SDIP-24 |
| 文件頁數(shù)： | 2/22頁 |
| 文件大小： | 157K |
| 代理商： | LC72146 |
Table 1 Input Data Functions
No. 4922-10/22
LC72146, 72146M, 72146V
No.
Name
Function
Related bits
Programmable divider ratio
P15 is the MSB. The divider ratio, frequency range and LSB are determined by the setting of the DVS and
SNS flags as shown in Table 2 and Table 3. P0 to P3 are ignored if P4 is the LSB.
Table 2 Divider ratio settings
Note:
× = don’t care
Table 3 Frequency range settings
Note:
× = don’t care
Sub-charge pump control
Bits PDC0 and PDC1 control the charge pump state as shown in Table 4. The sub-charge pump is
connected to the gate of the low-pass filter transistor. This can be used in conjunction with PD0 and PD1
(main charge pump) to build a fast locking PLL.
Table 4 Charge pump state selection
Note:
× = don’t care
* See the “Charge Pump” on page 16 for details.
Reference frequency select
Bits R0 to R3 disable the PLL or select the reference frequency as shown in Table 5.
Table 5 Reference frequency selection
When the PLL is disabled, the programmable divider is stopped, AMIN and FMIN are pulled to ground,
and the charge-pump outputs become high impedance.
DVS
SNS
LSB
Divider ratio (N)
1
×
P0
272 to 65535
0
1
P0
272 to 65535
0
P4
4 to 4095
DVS
SNS
Input port
Input frequency range (MHz)
1
×
FMIN
10 to 160
0
1
AMIN
2 to 40
0
AMIN
0.5 to 10
PDC1
PDC0
Charge pump state
0
×
High impedance
1
Operating (operates continuously)
1
0
Operating (when PLL is unlocked)
R3
R2
R1
R0
Reference frequency (kHz)
0
100
0
1
50
0
1
0
25
0
1
25
0
1
0
12.5
0
1
0
1
6.25
0
1
0
3.125
0
1
3.125
1
0
10
1
0
1
9
1
0
1
0
5
1
0
1
0
3
1
0
1
30
1
0
PLL inhibited and crystal oscillator stopped
1
PLL inhibited
P0 to P15,
DVS, SNS
(1)
PDC0,
PDC1
(2)
R0 to R3
(3)
UL0, UL1, DLC
Continued on next page.
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| LC72146V | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| LC72146M | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| LC72147V | PLL FREQUENCY SYNTHESIZER, 180 MHz, PDSO24 |
| LC72148V | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC72146M | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning |
| LC72146MA-AH | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| LC72146MHSQR-U-TRM-E | 制造商:Sony Semiconductor Solutions Division 功能描述: |
| LC72146V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| LC72147V | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning in Car Audio Systems |
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