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參數資料
| 型號： | LC72144M |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁數： | 4/22頁 |
| 文件大?。?/td> | 307K |
| 代理商： | LC72144M |
Continued from preceding page.
No. 5377-12/22
LC72144M
No.
Control section/
Function
Related data
data
General-
purpose
counter control
data
CTS0, CTS1,
CTE, GT0, GT1
CTP, CTC
I/O port control
data
I/O-0 to I/O-5
Output port
data
OUT0 to OUT5
General-
purpose
counter input
control data
H/I-6, L/I-7
Unlock
detection data
UL0, UL1
(6)
(7)
(8)
(9)
(10)
H/I-6, L/I-7
OUT0 to OUT5, ULD
I/O-0 to I/O-5, ULD
CTS0, CTS1
ULD, DT0, DT1
Data that selects the input pin (HCTR or LCTR) for the general-purpose counter
Data that specifies the start of a general-purpose counter measurement operation
CTE = 1: Count start
= 0: Count reset
Data that determines the general-purpose counter measurement time (in frequency mode) and number
of periods (in period mode)
CTP = 0: The general-purpose counter input is pulled down at count reset time (when CTE = 0).
= 1: The wait time is shortened by not pulling down the general-purpose counter input count reset
time (when CTE = 0). However, immediately after CTP is set to 1, the system must wait until
the general-purpose counter input pin is biased before starting a count.
The input sensitivity is lowered by setting CTC to 1. (Sensitivity: 10 to 30 mVrms)
Data that specifies the input or output state of the I/O ports
Data value = 0: Input port
= 1: Output port
Note: I/O-0, I/O-1, I/O-2, I/O-4, and I/O-5 are set to function as input ports after the power on reset.
I/O-3 is set to function as an output port after the power on reset.
Data that determines the output values of output ports O-0 to O-5
Data value = 1: Open or high
= 0: Low
Note: This data is invalid when the corresponding port is specified to function as an input port or as an
unlock state output.
Data that sets the general-purpose counter pins to function as input ports
H/I-6 = 0: I-6 (input port)
= 1: HCTR (general-purpose counter)
L/I-7 = 0: I-7 (input port)
= 1: LCTR (general-purpose counter)
Data that selects the phase error (E) detection width used for PLL lock state discrimination
If a phase error in excess of the E detection width listed in the table below is detected, the system
considers a phase error to have occurred and the PLL to be in the unlocked state. The detection pin
(DO or I/O-5) is set low in the unlocked state.
CTS1
CTS0
Input pin
Measurement mode
1
!
HCTR
Frequency
0
1
LCTR
Frequency
0
LCTR
Period
UL1
UL0
E detection width
Detection pin output
0
Stopped
Open
0
1
0
E output
1
0
±0.5 s
E with 1 to 2 ms expansion
1
±1.0 s
E with 1 to 2 ms expansion
Frequency measurement mode
Period measurement
GT1
GT0
Measurement time
Wait time (ms)
mode
(ms)
CTP = 0
CTP = 1
0
4
3 to 4
1 to 2
1 period
0
1
8
3 to 4
1 to 2
1 period
1
0
32
7 to 8
1 to 2
2 periods
1
64
7 to 8
1 to 2
2 periods
Continued on next page.
Expansion
Unlock state output
1 to 2 ms
I/O-5
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