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參數(shù)資料
| 型號： | LC72133V |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁數(shù)： | 10/23頁 |
| 文件大?。?/td> | 147K |
| 代理商： | LC72133V |
Unlock Detection Timing
1. Unlock Detection Determination Timing
Unlocked state detection is performed in the reference frequency (fref) period (interval). Therefore, in principle,
unlock determination requires a time longer than the period of the reference frequency. However, immediately after
changing the divisor N (frequency) unlock detection must be performed after waiting at least two periods of the
reference frequency.
Figure 1 Unlocked State Detection Timing
For example, if fref is 1 kHz, i.e., the period is 1 ms, after changing the divisor N, the system must wait at least 2 ms
before checking for the unlocked state.
Figure 2 Circuit Structure
No. 5427-18/23
LC72133M, 72133V
A11936
CE
DATA
LATCH
VCO/N
N-
counter
fref
÷R
÷N
DATA LATCH
VCO
Preset
fref
VCO/N
UNLOCK
L. P. F
A11937
ERROR
(unlock)
Old data
New data
Old divisor N
New divisor N'
The divisor N is not updated
in the first period.
Note: After changing the divisor, ERROR
is output after two fref periods.
Unlock
detection circuit
Phase comparator
ERROR
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