- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄43903 > LC72131M PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20 PDF資料下載
參數(shù)資料
| 型號(hào)： | LC72131M |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20 |
| 封裝： | MFP20 |
| 文件頁(yè)數(shù)： | 10/23頁(yè) |
| 文件大?。?/td> | 405K |
| 代理商： | LC72131M |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)當(dāng)前第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)
Unlock Detection Timing
1. Unlock Detection Determination Timing
Unlocked state detection is performed in the reference frequency (fref) period (interval). Therefore, in principle,
unlock determination requires a time longer than the period of the reference frequency. However, immediately after
changing the divisor N (frequency) unlock detection must be performed after waiting at least two periods of the
reference frequency.
Figure 1 Unlocked State Detection Timing
For example, if fref is 1 kHz, i.e., the period is 1 ms, after changing the divisor N, the system must wait at least 2 ms
before checking for the unlocked state.
Figure 2 Circuit Structure
No. 4921-18/23
LC72131, 72131M
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LC72134M | PLL FREQUENCY SYNTHESIZER, 160 MHz, PDSO24 |
| LC72135M | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20 |
| LC72136NM | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| LC72140M | PLL FREQUENCY SYNTHESIZER, 160 MHz, PDSO24 |
| LC72140 | PLL FREQUENCY SYNTHESIZER, 160 MHz, PDIP24 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC72131MDTRM | 制造商:Panasonic Industrial Company 功能描述:IC |
| LC72132 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:AM/FM PLL Frequency Synthesizer |
| LC72132M | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:AM/FM PLL Frequency Synthesizer |
| LC72133M | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning |
| LC72133M_11 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。