參數資料
型號: LC72130
廠商: Sanyo Electric Co.,Ltd.
英文描述: AM/FM PLL Frequency Synthesizers(AM/FM鎖相環(huán)頻率合成器)
中文描述: 調幅/調頻鎖相環(huán)頻率合成器(調幅/調頻鎖相環(huán)頻率合成器)
文件頁數: 10/22頁
文件大?。?/td> 306K
代理商: LC72130
2. DI Control Data Functions
No. 4973-10/22
LC72130, 72130M
No.
Control block/data
Functions
Related data
Programmable divider data Sets the programmable divider divisor.
P0 to P15
This value is a binary value whose MSB is P15. The position of the LSB varies
depending on DVS and SNS. (
*
: don’t care)
Note: P0 to P3 are ignored when P4 is the LSB.
DVS, SNS
These bits select the signal input pin for the programmable divider and switch the input
frequency range. (
*
: don’t care)
Note: See the “Programmable Divider” item for more information.
Reference divider data
R0 to R3
Selects the reference frequency (fref).
Note: PLL INHIBIT
The programmable divider block and the IF counter block are stopped, the FMIN,
AMIN, and IFIN pins are set to the pull-down state (ground), and the charge pump
goes to the high impedance state.
XS
Crystal resonator selection
XS = 0: 4.5 MHz
XS = 1: 7.2 MHz
The 7.2 MHz frequency is selected after the power ON reset.
IF counter control data
CTE
IF counter measurement start data
CTE = 1: Counter start
CTE = 0: Counter reset
GT0, GT1
Determines the IF counter measurement period.
Note: See the “IF Counter” item for more information.
I/O port specification data
IOC1, IOC2
Specifies the I/O direction for the bidirectional pins IO1 and IO2.
Data: 0 = input mode, 1 = output mode
Output port data
BO1 to BO5, IO1, IO2
Data that determines the output from the BO1 to BO5, IO1 and IO2 output ports
Data: 0 = open, 1 = low
The data = 0 (open) state is selected after the power ON reset.
(1)
(2)
(3)
(4)
(5)
IOC1
IOC2
DVS
SNS
LSB
Divisor setting (N)
Actual divisor
1
*
P0
272 to 65535
Twice the value of the setting
0
1
P0
272 to 65535
The value of the setting
0
0
P4
4 to 4095
The value of the setting
DVS
SNS
Input pin
Input frequency range
1
*
FMIN
10 to 160 MHz
0
1
AMIN
2 to 40 MHz
0
0
AMIN
0.5 to 10 MHz
GT1
GT0
Measurement time (ms)
Wait time (ms)
0
0
4
3 to 4
0
1
8
3 to 4
1
0
32
7 to 8
1
1
64
7 to 8
R3
R2
R1
R0
Reference frequency (kHz)
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
100
50
25
25
12.5
6.25
3.125
3.125
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
10
9
5
1
1
1
1
1
0
0
0
1
3
15
1
1
1
0
PLL INHIBIT + X’tal OSC STOP
1
1
1
1
PLL INHIBIT
Continued on next page.
IFS
相關PDF資料
PDF描述
LC72131 AM/FM PLL Frequency Synthesizers(AM/FM鎖相環(huán)頻率合成器)
LC72132 AM/FM PLL Frequency Synthesizers(AM/FM鎖相環(huán)頻率合成器)
LC72133M PLL Frequency Synthesizer for Electronic Tuning(用于電子調諧的鎖相環(huán)頻率合成器)
LC72134M Dual PLL Frequency Synthesizer for FM Tuner Systems(用于FM調諧器的雙鎖相環(huán)頻率合成器)
LC72135M PLL Frequency Synthesizer for Electronic Tuning(用于電子調諧的鎖相環(huán)頻率合成器)
相關代理商/技術參數
參數描述
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LC72130M 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:AM/FM PLL Frequency Synthesizer
LC72131 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:AM/FM PLL Frequency Synthesizer
LC72131D 制造商:Panasonic Industrial Company 功能描述:IC