參數(shù)資料
型號: LC72122V
廠商: SANYO SEMICONDUCTOR CO LTD
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20
封裝: SSOP-20
文件頁數(shù): 19/22頁
文件大小: 346K
代理商: LC72122V
No. 6113-6/22
LC72122V
Continued from preceding page.
Symbol
Pin No.
Type
Functions
Circuit configuration
5
6
7
8
9
15
16
17
18
10
BO1
BO2
BO3
IO1
IO2
PD
AIN
AOUT
Vssa
Output ports
Input or output
ports
Charge pump
output
LPF amplifier
transistor
connections
IF counter
Dedicated outputs
The output states are determined by the BO1 to BO3
bits in the serial data.
Data: 0 = open, 1= low
A time base signal (8 Hz) can be output from the BO1
pin. (When the serial data TBC bit is set to 1.)
I/O dual-use pins
The direction (input or output) is determined by bits IOC1
and IOC2 in the serial data.
Data: 0 = input port, 1 = output port
When specified for use as input ports:
The state of the input pin is transmitted to the controller
over the DO pin.
Input state: low = 0 data value
high = 1 data value
When specified for use as output ports:
The output states are determined by the IO1 and IO2
bits in the serial data.
Data: 0 = open, 1 = low
These pins function as input pins following a power on
reset.
PLL charge pump output
When the frequency generated by dividing the local
oscillator signal frequency by N is higher than the
reference frequency, a high level is output from the PD
pin. Similarly, when that frequency is lower, a low level is
output. The PD pin goes to the high-impedance state
when the frequencies match.
The n-channel MOS transistor used for the PLL active
low-pass filter.
The AIN pin is connected internally to a fast locking sub-
charge pump circuit (PDS).
Vssa is special-purpose ground pin.
Accepts an input in the frequency range 0.4 to 12 MHz.
The input signal is directly transmitted to the IF counter.
The result is output starting the MSB of the IF counter
using the DO pin.
Four measurement periods are supported: 8, 16, 32, and
64 ms.
IFIN
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