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參數(shù)資料
| 型號： | LC72121V |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | PLL Frequency Synthesizers for Electronic Tuning(用于電子調(diào)諧的鎖相環(huán)頻率合成器) |
| 中文描述： | 鎖相環(huán)頻率合成器電子調(diào)諧（用于電子調(diào)諧的鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 11/23頁 |
| 文件大?。?/td> | 375K |
| 代理商： | LC72121V |
No.
Control block/data
Function
Related data
No. 5815-11/23
LC72121, 72121M, 72121V
Continued from preceding page.
No.
Control block/data
Function
Related data
9
Clock time base
TBC
Setting the TBC bit to 1 causes an 8-Hz clock time base signal with a 40% duty to be output from the
BO1 pin. (The BO1 data will be ignored.)
BO1
10
Charge pump
control data
DLC
Forcibly controls the charge pump output.
*
If the circuit deadlocks due to the VCO control voltage (Vtune) being 0 and the VCO being stopped,
applications can get out of the deadlocked state by setting the charge pump output to low and setting
Vtune to V
CC
. (Deadlock clear circuit)
11
IF counter control
data
IFS
This data is normally set to 1. Setting this data to 0 sets the circuit to reduced input sensitivity mode, in
which the sensitivity is reduced by about 10 to 30 mV rms.
*
See the “IF Counter Operation” section for details.
1
I/O port data
12, I1
Data latched from the I/O port IO1 or IO2 pin states.
These bits reflect the pin states regardless of the I/O port mode (input or output).
The data is latched at the point the circuit enters data output mode (OUT mode).
I1
←
The IO1 pin state
H : 1
I2
←
The IO2 pin state
L : 0
IOC1
IOC2
12
Test data
TEST0 to 2
Test data
TEST0
TEST1
TEST2
All these bits are set to 0 after a power on reset.
All these bits must be set to 0.
13
DNC
This bit must be set to 0.
DLC
Charge pump output
0
Normal operation
1
Forced to low
Structure of the DO Output Data (serial data output)
OUT mode
DO Output Data
2
PLL unlocked state
data
UL
Indicates the state of the unlocked state detection circuit.
UL
←
0: When the PLL is unlocked.
UL
←
1: When the PLL is locked or in the detection disabled mode.
UL0
UL1
3
IF counter binary
data
C19 to C0
Indicates the value of the IF counter (20-bit binary counter).
C19
←
MSB of the binary counter
C0
←
LSB of the binary counter
CTE
GT0
GT1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LC72121 | PLL Frequency Synthesizers for Electronic Tuning |
| LC72121M | PLL Frequency Synthesizers for Electronic Tuning |
| LC72122V | PLL Frequency Synthesizer for Portable Equipment Electronic Tuning |
| LC72130 | AM/FM PLL Frequency Synthesizers(AM/FM鎖相環(huán)頻率合成器) |
| LC72131 | AM/FM PLL Frequency Synthesizers(AM/FM鎖相環(huán)頻率合成器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC72121V-D-MPB-E | 制造商:ON Semiconductor 功能描述:PLL FREQUENCY SYNTHESIZER - Ammo Pack |
| LC72121V-D-TLM-E | 制造商:ON Semiconductor 功能描述:PLL FREQUENCY SYNTHESIZER - Tape and Reel |
| LC72121V-TLM-E | 功能描述:時(shí)鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| LC72122V | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Portable Equipment Electronic Tuning |
| LC72122V-MPB-E | 制造商:ON Semiconductor 功能描述:PLL FREQUENCY SYNTHESIZER - Ammo Pack |
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