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參數(shù)資料
| 型號： | LC7153M |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 160 MHz, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大小： | 279K |
| 代理商： | LC7153M |
LC7153, 7153M
No.4160–5/11
Serial Data Input Timing
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Functional Description
PLLA and PLLB Programmable Dividers
PLLA and PLLB input frequency ranges are set by Mode 2
command bits FA and FB, respectively. Their divider ra-
tios, NA and NB, are set by Mode 1 command bits DA0 to
DA15 and DB0 to DB15, respectively.
Programmable Reference Divider
The divider ratio, NR, is set by Mode 2 command bits R0
to R13. The reference frequency is given by fXIN/(2×NR).
Phase Detector
The state of the phase-detector output as a function of the
divider ratio and reference frequency is shown in table 1.
Table 1. Phase-detector output states
Note
N=NA for PLLA, and NB for PLLB
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When PLLA is unlocked, LDA is pulled LOW and both
PDA1 and PDA2 are active. PLLB operates identically to
PLLA. Mode 2 command bits UL0 and UL1 set the unlock
phase-error threshold, and bits UE0 and UE1, the LDA and
LDB output extension.
Dual Charge Pump
A typical dual charge-pump configuration is shown in fig-
ure 1. The phase-detector secondary output is active after a
change in frequency, and the phase error causes the PLL to
unlock. In this case, the load resistance R1 becomes
R1M||R1S, decreasing the LPF time constant and the time
required to lock the PLL.
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