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參數(shù)資料
| 型號(hào)： | LC7152NM |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 55 MHz, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁(yè)數(shù)： | 8/11頁(yè) |
| 文件大?。?/td> | 287K |
| 代理商： | LC7152NM |
Continued from preceding page.
Symbol
Pin No.
Function
Description of function
CE
*1
2
Chip enable input
.
Set this pin high when inputting serial data to the LC7152.
CL
*1
3
Clock input
.
Clock for data synchronization when inputting serial data to the LC7152.
DI
*1
4
Data input
.
Input for serial data being sent from the controller to the LC7152.
VDD
VSS
17
15
Power supply
Ground
.
LC7152 power supply pin.
TEST
8
IC Test input
.
LC7152 test pin. (Normally VSS or open.)
.
However, divide-by-two XIN frequency is output from the pin OUTA by
applying the VDD level voltage after serial data transfer (T0 = T1 = T2 = 0).
Crystal oscillation frequency can be checked normally when the pin is left
open.
*1 The input ‘‘H’’ voltage and the input ‘‘L’’ voltage on the CE, CL, and DI pins are VIH = 1.5 to 5.5V and VIL = 0 to 0.4V
when VDD = 2.0V. When VDD = 3.3V, then VIH = 1.7 to 5.5V and VIL = 0 to 0.6V. (Voltage greater than VDD may be applied
to VIH.)
Serial Input Data (PLL Control data) format
Mode1: Latch-1 data (programmable divider data)
Mode data
Control data
LC7152, 7152M, 7152NM, 7152KM
No.3889-6/13
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