參數(shù)資料
型號: LC680100A
廠商: Sanyo Electric Co.,Ltd.
英文描述: 32-Bit RISC Microcontroller
中文描述: 32位RISC微控制器
文件頁數(shù): 5/16頁
文件大?。?/td> 894K
代理商: LC680100A
LC680100A
No.6830-5/16
Pin Number
Pin Name
I/O
Function Description
Pin Format
33
NMI
I
NMI interrupt
Schmitt Input
35
P10/
BGNT
I/O
PORT1 bit0 input.
Also bus grant output.
PORT1 bit1 input. Also
DRAM control RAS signal out.
PORT1 bit2 input. Also
DRAM control CASU signal out.
PORT1 bit3 input. Also
DRAM control CASL signal out.
PORT1 bit4 input. Also
DRAM control DMXS signal out.
PORT1 bit5 input. Also
DRAM control RFREQ I/O.
PORT1 bit6 input.
Also IRQOT output.
PORT1 bit7 input.
MCLK output,
HOLD state output
Bus Address bit0 or
Lower byte strobe signal.
Bus Address bit1 to 24.
36
P11/
RAS
I/O
37
P12/
CASU
I/O
38
P13/
CASL
I/O
39
P14/
DMXS
I/O
Schmitt InputTristate
output
40
P15/
RFREQ
I/O
Schmitt InputPU
Output
Schmitt InputTristate
output
41
42
P16/
IRQOT
I/O
P17/MCLK/
HOLD0
I/O
44
A0/
LBS
I/O
45 to 54,
56 to 69
70
A1to A24
I/O
A25/
CS5
I/O
Bus Address bit25 or CS5.
71
A26/
CS4
I/O
Bus Address bit26 or CS4
72
A27/
CS3
I/O
Bus Address bit27 or CS3.
Schmitt InputTristate
output
74 to 81,
83 to 90
92
D0 to D15
I/O
Bus data bit0 to 15
Schmitt InputTristate
output
Schmitt InputTristate
output
CS0
I/O
CS0
93
CS1
I/O
CS1
94
CS2
I/O
CS2
95
CS6
I/O
CS6
Bus read signal.
96
RD
I/O
97
WRU
/
UBS
I/O
Upper byte write signal or Upper byte strobe.
98
WRL
/
WR
I/O
Upper byte write signal or Write.
Schmitt InputTristate
output
99
WAIT
I/O
Bus cycle wait
Schmitt InputPU
output
Schmitt Input
100
BREQ
I
Bus request.
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