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參數(shù)資料
| 型號(hào)： | LC5852N |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Four-Bit Single-Chip Microcontroller with On-Chip LCD Drivers for Small-Scale Control in Medium-Speed Applications(應(yīng)用于中等速率中小規(guī)?？刂频?位微控制器（帶片上LCD驅(qū)動(dòng)器）) |
| 中文描述： | 4位單片微控制器，帶有片上LCD驅(qū)動(dòng)器的小規(guī)模控制在中速應(yīng)用（應(yīng)用于中等速率中小規(guī)?？刂频?位微控制器（帶片上液晶驅(qū)動(dòng)器）） |
| 文件頁(yè)數(shù)： | 12/29頁(yè) |
| 文件大?。?/td> | 356K |
| 代理商： | LC5852N |
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Internal Register Functions
No. 4365-12/29
LC5852N
Symbol
R/W
Function
Initialization
value at reset
PC
ROM
RAM
—
R/O
R/W
Program counter
The PC is an 11-bit counter that specifies the program memory (ROM) address of the next instruction to
be executed.
Normally, the PC is incremented on each instruction execution, from 000H to 7FFH. However, when a
branch or subroutine call is executed, or when an interrupt or initializing reset occurs, the PC is set to a
value corresponding to the particular operation. The table below shows how the PC is set for these
operations.
Page:
ROM paging performed in 1024 word pages
Pages are specified with the SF and RF instructions.
Instruction code bits (immediate data)
P0 – P9:
Program memory
The on-chip ROM consists of 2048 15-bit words and holds the user programs to be executed.
Data memory
The on-chip RAM consists of 128 4-bit digits of static RAM in two pages with 64 4-bit digits per page.
This RAM has the following features:
RAM addresses can be specified directly (immediate addressing) as values in the range 00H to 3FH.
Arithmetic operations can be performed between the AC and any RAM location.
Due to the provision of the segment PLA circuit, RAM dedicated to display is not required.
RAM locations 38H to 3FH have a function that allows direct arithmetic operations with other data
without using the AC.
The AC is used for RAM input, i.e., writing.
Undefined
PC
PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Operation
Initializing reset
0
0
0
0
0
0
0
0
0
0
0
INT pin external interrupt
0
0
0
0
0
0
1
0
0
0
0
S or M port external
interrupt
0
0
0
0
0
0
1
0
1
0
0
Timer internal interrupt
0
0
0
0
0
0
1
1
0
0
0
Divider internal interrupt
0
0
0
0
0
0
1
1
1
0
0
Unconditional jump (JMP)
Page
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
Conditional jump
(BAB0, BAB1, BAB2, BAB3, Page
BAZ, BANZ, BCH, BCNH)
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
Subroutine call instruction
(CALL)
Page
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
Return instruction
(RTS, RTSR)
CALL address + 1
Continued on next page.
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