• 參數(shù)資料
    型號(hào): LC4256V-5F256AI
    文件頁數(shù): 30/57頁
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    代理商: LC4256V-5F256AI
    Lattice Semiconductor
    ispMACH 4000V/B/C Family Data Sheet
    30
    Signal Descriptions
    Signal Names
    Description
    TMS
    Input – This pin is the IEEE 1149.1 Test Mode Select input, which is used to control
    the state machine
    Input – This pin is the IEEE 1149.1 Test Clock input pin, used to clock through the
    state machine
    Input – This pin is the IEEE 1149.1 Test Data In pin, used to load data
    Output – This pin is the IEEE 1149.1 Test Data Out pin used to shift data out
    Input – These pins are the Global Output Enable Input pins
    Ground
    Not Connected
    The power supply pins for logic core
    These pins are con
    fi
    gured to be either CLK input or as an input
    The power supply pins for each I/O bank
    Input/Output
    1
    – These are the general purpose I/O used by the logic array. y is GLB
    reference (alpha) and z is macrocell reference (numeric). z: 0-15
    ispMACH 4032
    ispMACH 4064
    ispMACH 4128
    ispMACH 4256
    ispMACH 4384
    ispMACH 4512
    TCK
    TDI
    TDO
    GOE0, GOE1
    GND
    NC
    V
    CC
    CLK0/I, CLK1/I, CLK2/I, CLK3/I
    V
    CCO0
    , V
    CCO1
    yzz
    y: A-B
    y: A-D
    y: A-H
    y: A-P
    y: A-P, AX-HX
    y: A-P, AX-PX
    1. In some packages, certain I/O are only available for use as inputs. See the signal connections table for details.
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