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參數(shù)資料
| 型號： | LC201V02-A3 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 20.1 VGA TFT LCD |
| 中文描述： | 20.1顯卡液晶 |
| 文件頁數(shù)： | 11/26頁 |
| 文件大?。?/td> | 456K |
| 代理商： | LC201V02-A3 |
Product Specification
11 / 26
LC201V02
Liquid Crystal Display
Ver. 0.1
Jan. 17, 2003
3-3. Signal Timing Specifications
Table 5. Timing Table
This is the signal timing required at the input of the User connector. All of the interface signal timing should be
satisfied with the following specifications for it’s proper operation.
-
-
3
t
HI
DE HOLD TIME
ns
-
-
3
t
SI
DE SET UP TIME
V
-
-
0.7Vcc
V
rH
High
Input
Voltage
0.3Vcc
-
-
V
rL
Low
3
t
HD
Hold time
For DCLK
ns
3
t
SD
Set-up time
Data
MHz
30
25
18
-
Frequency
ns
-
-
10
t
WCH
High Duration
33
33
3
t
VBP
Vertical Back Porch
t
HP
480
480
480
t
VV
Vertical Valid
tHP-THV
-
150
-
Horizontal Blank
-
16
16
t
HFP
Horizontal Front Porch
tVP-tVV
-
10
-
Vertical Blank
-
9
2
t
VFP
Vertical Front Porch
DE
(Data
Enable)
NTSC:57~ 63Hz
t
HP
t
CLK
t
CLK
48
48
16
t
HBP
Horizontal Back Porch
Hz
63
60
47
fV
Frequency
3
3
2
t
WV
Width
96
96
16
t
WH
Width
t
CLK
850
800
790
t
HP
Period
Hsync
PAL: 47~ 53Hz
t
HP
560
525
490
t
VP
Period
Vsync
640
640
640
t
HV
Horizontal Valid
ns
-
-
10
t
WCL
Low Duration
ns
55
40
33.3
t
CLK
Period
DCLK
Note
Unit
Max
Typ
Min
Symbol
ITEM
Note
:
Hsync period and Hsync width-active should be even number times of t
CLK
. If the value is odd number times
of t
CLK
, display control signal can be asynchronous. In order to operate this LCM a
Hsync
, Vsync and DE
(Data Enable) signals should be used.
1. The performance of the electro-optical characteristics
may
be influenced by variance of the vertical
refresh rates.
2. Vsync, Hsync should be keep the above specification.
3. Hsync Period,
Hsync
Width and Horizontal Back Porch should be any times of a character number (8).
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