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Analog Line Scan Cameras
www.perkinelmer.com/opto
DSP-205.01A - 4/2001W Page 2
The Sensor
LC1917-series cameras contain a
high-performance, high-resolution line
scan image sensor (PerkinElmer
Optoelectronics parts RL1024PAG)
featuring a pinned photodiode pixel.
Each photodiode converts incident
light into discrete charge packets.
Advantages of pinned photodiode
pixels include linear exposure control,
the elimination of image lag, and the
reduction of photo response non-
uniformity (PRNU). For more specific
sensor specifications and information,
please consult the appropriate sensor
datasheet, available by contacting
PerkinElmer. Figure 1a details the
spectral sensitivity of the sensor,
while Figure 1b details the sensor’s
glass window light transmission curve.
Functional Description
The video signal from the sensor is
processed through a single channel of
sampled-and-held, raster order, analog
video data. The video channel signal
processing circuitry offers both
adjustable gain and dark offset levels
to allow customization of the camera
to unique lighting applications. An
operational amplifier in a differential
configuration is recommended to
receive the video signal. Figure 2
details the camera video processing.
Input Signals
The LC1917 camera requires DC supply
voltages of +12 VDC, -12 VDC, and
+5 VDC for operation. Table 3 further
describes power requirements and
voltages, along with tolerances. By
default, the camera will operate at its
maximum line rate of 4700 scans per
second. The camera is controlled by
two externally generated differential
input signals: Master Clock (MCLK)
and Line Transfer (LT).
The Master Clock input determines
the data rate frequency for values up to
maximum clock of the camera (5 MHz).
The data rate may be run from 1 MHz
to cameras maximum clock rate.
The LT input signal transfers the
charge from each photosite to the
readout registers. The readout
registers, in turn, transport the charge
from each photodiode in succession to
the video outputs. The LT input from
the user must remain in the ON state
for at least one and a half MCLK
cycles to initiate the internal line
transfer and may remain ON until one
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μ
J
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Q
Right Scale
Left Scale
Figure 1a. Spectral Sensitivity Curve (1X Gain)
Figure 1b. Sensor Window Transmission Curve
Figure 2. Camera Block Diagram
Line Transfer Logic
Line Enable Logic
FPGA
MCLK
Logic
Drive
Logic
LT
LEN
L
T
CLT+
CLT-
IMAGER
Bufer
Offset
ADJ
Gain
ADJ
Sample -
and - Hold
Amp
LENS
LEN+
LEN-
CCLK+
CCLK-
V
OUT+
V
OUT-
LT+
LT-
MCLK+
MCLK-
+12VDC
+5VDC
-12VDC
H
1
H
2
PG
RG
TG
AB
VIDEO