參數(shù)資料
型號(hào): LC11011-141
廠商: Sanyo Electric Co.,Ltd.
英文描述: Computer Image Signal Processing Full-Color Gray-Scale Processor
中文描述: 計(jì)算機(jī)圖像信號(hào)處理全彩色灰度處理器
文件頁數(shù): 5/7頁
文件大?。?/td> 148K
代理商: LC11011-141
No. 5041-5/7
LC11011-141
Pin Functions
Symbol
Pin No.
I/O
Function
V
DD
5, 21, 28, 32, 41,
61, 68, 91
Input
Power supply (+5 V)
10, 15, 20, 26, 30,
34, 35, 40, 46,51,
56, 66, 71, 73, 82,
87, 90, 98
V
SS
Input
GND (0 V)
NC
24, 76, 77
Must be left open.
MODESEL0
1
Input
MODESEL1
2
Input
MODESEL2
3
Input
MODESEL3
4
Input
Input bypass pin. When this pin is low, the LC11011-141 performs no gray scale processing, but rather
simply passes the input signals through unchanged. When a low level input on this pin is sampled on the
rising edge of the clock, the IC will begin the output of unchanged data two clock cycles later.
BYPASS
100
Input
TEST0
6
Input
TEST1
7
Input
Test pins [0:3]; left open in normal operation.
TEST2
8
Input
TEST3
9
Input
SCLK
67
Input
Display dot clock input. Data is processed according to this clock signal.
SRDATA [0:7]
57 to 60, 62 to 65
Input
Input pins for red, green and blue scale data. SRDATA7, SGDATA7, and SBDATA7 are the MSBs.
SRDATA0, SGDATA0, and SBDATA0 are the LSBs.
SGDATA [0:7]
78 to 81, 83 to 86
Input
SBDATA [0:7]
88, 89, 92 to 97
Input
Shsync
69
Input
Horizontal and vertical synchronization signal inputs. These are the sources for the Hsync and Vsync
signals. These are also used to control data processing. These are low level active signals.
Svsync
70
Input
Horizontal data valid period signal input. Set this pin high during periods when the horizontal data is
valid. If this signal is not used, tie it high, and set the input data to zero during the horizontal blanking
period.
SHDEN
72
Input
SCTL0
74
Input
LCD control inputs. Input control signals that must be matched to the data signal timing. These are the
sources for the CTL signals. If the CTL [0:1] signals are not used, there is no need to input the
SCTL [0:1] signals.
SCTL1
75
Input
CLKSEL
99
Input
CLKSEL is the dot clock output selection. It is used to select the output mode of the dot clock signal
output pin.
If CLKSEL is low: A signal with the same phase as the SCLK pin is output from the CLK pin.
If CLKSEL is high: A signal with the opposite phase from the SCLK pin is output from the CLKB pin.
CLK
31
Output
CLKB
33
Output
Mode selection signals [0:3] for the gray scale mode.
The setting process for the mode selection lines is described below.
MODESEL0 is the LSB, and MODESEL3 is the MSB.
Note that modes 8, 9, C, D and E are compatible with the LC1001-131 (a product that handles 6-bits
of input for each of the RGB signals).
Note: Do not use gray scale modes 0, 1, 3, 8 and 9 with LCD modules that perform FRC or other inter-
frame processing.
Note: Y = yes, N = no, R = reserved
Color scale mode
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
MODESEL0
MODESEL1
MODESEL2
MODESEL3
L
L
L
L
H
L
L
L
L
H
L
L
H
H
L
L
L
L
H
L
H
L
H
L
L
H
H
L
H
H
H
L
L
L
L
H
H
L
L
H
L
H
L
H
H
H
L
H
L
L
H
H
H
L
H
H
L
H
H
H
H
H
H
H
Intra-frame
processing
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
R
R
R
R
R
Processing
Inter-frame
processing
Y
Y
Y
N
N
N
Y
Y
N
N
N
Number of valid input bits
8
8
8
8
8
8
6
6
6
6
6
Number of output bits
3
4
6
4
5
6
3
4
3
4
5
Gray scale modes 0, 8 and C
Operating mode for TFT-LCD modules using 3-bit source drivers.
Gray scale modes 1 and 9
Operating mode for TFT-LCD modules using 4-bit source drivers.
Gray scale mode 3
Operating mode for TFT-LCD modules using 6-bit source drivers.
Gray scale modes 5 and D
Operating mode for TFT-LCD modules that perform
FRC or other inter-frame processing.
Gray scale modes 6, 7 and E
Operating mode for TFT-LCD modules that perform FRC or other
inter-frame processing.
Continued on next page.
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