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參數(shù)資料
| 型號(hào)： | LB11690 |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | BRUSHLESS DC MOTOR CONTROLLER, 0.04 A, PDIP30 |
| 封裝： | 0.400 INCH, DIP-30 |
| 文件頁(yè)數(shù)： | 5/19頁(yè) |
| 文件大?。?/td> | 201K |
| 代理商： | LB11690 |
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3. PWM Oscillator Circuit
The PWM frequency is determined by the capacitor C (rated in F) connected to the PWM pin.
fPWM ≈ 1/(93000 × C)
When a 270 pF capacitor is used, the frequency will be about 39 kHz. If the PWM frequency is too low, the motor
will generate audible noise at the switching frequency, and if it is too high, the power loss will increase. A frequency
in the range 20 to 50 kHz is desirable. Connect the ground side of this capacitor to a point as close as possible to the
IC ground pin to minimize the influence of output noise.
4. Control Methods
The output duty is determined by comparing the PWM oscillator waveform to the TOC pin voltage. When the TOC
pin voltage is about 1.2 V or lower, the duty will be 0%, and when that voltage is 3.0 V or higher, the duty will be
100%.
Normally, the integrating amplifier is used as a full feedback amplifier (with
the EI– pin and the TOC pin connected directly), and the control voltage is
input to the EI+ pin. (Here, the output duty increases as the EI+ voltage
increases.) When the EI+ pin is set to the reset operating state by the RES pin,
the EI pin voltage is lowered to a level close to the ground level by an IC
internal transistor. (This is to discharge the capacitor.) Therefore, do not
connect a low-impedance power supply directly to this pin, but rather input
the voltage through a resistor. Also, a pull-down resistor must be inserted
between the EI+ pin and ground so that the motor does not operate when the
control voltage is in the open state. If there is noise on the control voltage or if
it is desirable to suppress rapid fluctuations in the control voltage, a noise
rejection capacitor must be inserted between the EI+ pin and ground. The
operating voltage range can be expanded by inputting the control voltage to
the EI+ pin through a resistor voltage divider as shown in the figure.
A speed control circuit using the FV pin can be implemented as shown in the
figure to control the motor so that a constant speed is maintained to a certain
degree despite variations in the load. A resistor of 25 k
or larger must be
used between the FV and EI+ pin. The feedback capacitor must be selected so
that the TOC pin voltage is adequately stable at low speeds.
5. Charge Pump Circuit
The charge pump steps up the supply voltage to generate the high side FET gate voltage. The capacitor CP connected
between the CP1 and CP2 pins is used for step up, and charge is stored on the capacitor CB connected between the
VB and VCC pins. The capacitances of CP and CB must have the following relationship.
CB
≥ CP × 4
The CP capacitor is charged and discharged based on the PWM frequency. While increasing the capacitance of the
capacitor C increases current capacity of the VB power supply, if the capacitance is too large, the charge and
discharge operation may be inadequate. Note that the larger the capacitance of the capacitor VB, the more stable the
VB voltage will be. However, if that capacitance is too large, the time before the VB voltage is generated when
power is first applied will increase. While testing and evaluation is required to set the values of the capacitors CP and
CB, use the following table as a reference for the initial values.
When the VCC supply voltage is under 20 V, the VB power supply current capacity falls rapidly causing the VB
voltage to fall. Care is required in application design to assure that this does not become a problem.
No. 7543-13/19
LB11690, 11690H
Control voltage
TOC
EI+
EI–
Control voltage
TOC
EI+
EI–
To the FV pin
VCC voltage
24 V
36 V
CP
0.1 F
6800 pF
CB
1 F
0.47 F
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