參數(shù)資料
型號(hào)： LAN8187-JT
廠商： STANDARD MICROSYSTEMS CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX
中文描述： 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, TQFP-64
文件頁(yè)數(shù)： 14/66頁(yè)
文件大小： 545K
代理商： LAN8187-JT
High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX
Datasheet
Revision 0.6 (02-24-06)
14
SMSC LAN8187/LAN8187I
DATASHEET
Table 3.2 LED Signals
SIGNAL NAME
TYPE
DESCRIPTION
CRS
O
Carrier Sense
: Indicates detection of carrier.
RX_DV
O
Receive Data Valid
: Indicates that recovered and decoded data
nibbles are being presented on RXD[3:0].
Note:
This signal is not used in RMII Mode.
SPEED100/
PHYAD0
I/O
LED1 –
SPEED100 indication. Active indicates that the selected
speed is 100Mbps. Inactive indicates that the selected speed is
10Mbps.
Note:
This signal is mux’d with PHYAD0
LINK/
PHYAD1
I/O
LED2 –
LINK ON indication. Active indicates that the Link
(100Base-TX or 10Base-T) is on.
Note:
This signal is mux’d with PHYAD1
ACTIVITY/
PHYAD2
I/O
LED3 –
ACTIVITY indication. Active indicates that there is
Carrier sense (CRS) from the active PMD.
Note:
This signal is mux’d with PHYAD2
FDUPLEX/
PHYAD3
I/O
LED4 –
DUPLEX indication. Active indicates that the PHY is in
full-duplex mode.
Note:
This signal is mux’d with PHYAD3
Table 3.3 Management Signals
SIGNAL NAME
TYPE
DESCRIPTION
MDIO
I/O
Management Data Input/OUTPUT
: Serial management data
input/output.
MDC
I
Management Clock
:
Serial management clock.
Table 3.4 Boot Strap Configuration Inputs
a
SIGNAL NAME
TYPE
DESCRIPTION
GPO1/
PHYAD4
I/O
PHY Address Bit 4:
set the
default address of the PHY. This
signal is mux’d with GPO1
FDUPLEX/
PHYAD3
I/O
PHY Address Bit 3:
set the
default address of the PHY.
Note:
This signal is mux’d with FDUPLEX
ACTIVITY/
PHYAD2
I/O
PHY Address Bit 2:
set the
default address of the PHY.
Note:
This signal is mux’d with ACTIVITY
LINK/
PHYAD1
I/O
PHY Address Bit 1:
set the
default address of the PHY.
Note:
This signal is mux’d with LINK
SPEED100/
PHYAD0
I/O
PHY Address Bit 0:
set the
default address of the PHY.
Note:
This signal is mux’d with SPEED100
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