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參數(shù)資料
| 型號： | LA4128V-75TN144E |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 23/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 128MACROCELLS 144TQFP |
| 標準包裝： | 60 |
| 系列： | LA-ispMACH |
| 可編程類型： | 系統(tǒng)內可編程 |
| 最大延遲時間 tpd(1)： | 7.5ns |
| 電壓電源 - 內部： | 3 V ~ 3.6 V |
| 宏單元數(shù)： | 128 |
| 輸入/輸出數(shù)： | 96 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應商設備封裝： | 144-TQFP（20x20） |
| 包裝： | 托盤 |
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
3
The I/Os in the LA-ispMACH 4000V/Z automotive devices are split into two banks. Each bank has a separate I/O
power supply. Inputs can support a variety of standards independent of the chip or bank power supply. Outputs
support the standards compatible with the power supply provided to the bank. Support for a variety of standards
helps designers implement designs in mixed voltage environments. In addition, 5V tolerant inputs are specied
within an I/O bank that is connected to VCCO of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces.
LA-ispMACH 4000V/Z Automotive Architecture
There are a total of two GLBs in the LA-ispMACH 4032V/Z, increasing to 8 GLBs in the LA-ispMACH 4128V/Z.
Each GLB has 36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into
the GRP to be connected to the inputs of any other GLB on the device. Even if feedback signals return to the same
GLB, they still must go through the GRP. This mechanism ensures that GLBs communicate with each other with
consistent and predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them
to the associated I/O cells in the I/O block.
Generic Logic Block
The LA-ispMACH 4000V/Z Automotive GLB consists of a programmable AND array, logic allocator, 16 macrocells
and a GLB clock generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O
pins are decoupled from macrocells through the ORP. Figure 2 illustrates the GLB.
Figure 2. Generic Logic Block
AND Array
The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are
used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con-
nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic
allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and
Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being
fed to the macrocells.
Every set of ve product terms from the 80 logic product terms forms a product term cluster starting with PT0.
There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND
Array.
Logic
Allocator
36 Inputs
from GRP
16
Macrocells
To
ORP
To GRP
To
Product Term
Output Enable
Sharing
1+OE
16
MC
Feedback
Signals
Clock
Generator
1+OE
CLK0
CLK1
CLK2
CLK3
1+OE
AND
Array
36
Inputs,
83
Product
Terms
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LA4128V-75TN44E | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4128V-75TN48E | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4128ZC-75TN100E | 功能描述:CPLD - 復雜可編程邏輯器件 Auto Grade (AEC-Q100 ) ispMACH4128Z RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| LA4128ZC-75TN128E | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4128ZC-75TN144E | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
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