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參數(shù)資料
| 型號： | L99PD08TR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY MANAGEMENT CKT, PQFP32 |
| 封裝： | ROHS COMPLIANT, LQFP-32 |
| 文件頁數(shù)： | 22/41頁 |
| 文件大?。?/td> | 750K |
| 代理商： | L99PD08TR |
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L99PD08
SPI
Doc ID 15872 Rev 3
29/41
hex32
STK_FAULT
Read/clear
STK ON/OLOFF failure register
hex33
OVL_FAULT
Read/clear
Overload failure register
Table 23.
RAM memory map (continued)
Address
Name
Access
Content
Table 24.
ROM memory map (access with OC0 and OC1 set to ‘1’)
Address
Name
Access
Content
0x00
ID header
Read only
hex43 (device class ASSP, 2 additional information bytes)
0x01
Version
Read only
hex00 (engineering samples) (ST-SPI)
0x02
ProducCode1
Read only
hex25 (ST-SPI)
0x03
ProducCode2
Read only
hex50 (ST-SPI)
0x3E
SPI frame ID
Read only
hex01 SPI-Frame-ID register (ST-SPI)
Table 25.
Control register, hex00 (RW-Type)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MUX_EN
MUX_C
MUX_B
MUX_A
CS_MON1
CS_MON0
-
LHOMEN
MUX_EN 0
the multiplexer MUX ST/CS pin is inactive (tristate)
1
the multiplexer MUX ST/CS pin is active (default)
MUX_A …MUX_C - STATUS/CSENSE multiplexer pin – selection of one signal (ST0/CS0
… ST7/CS7) to MUX ST/CS pin
MUX_C MUX_B MUX_A
0
ST0/CS0 signal is transferred to MUX ST/CS pin (default)
0
1
ST1/CS1 signal is transferred to MUX ST/CS pin
0
1
0
ST2/CS2 signal is transferred to MUX ST/CS pin
0
1
ST3/CS3 signal is transferred to MUX ST/CS pin
1
0
ST4/CS4 signal is transferred to MUX ST/CS pin
1
0
1
ST5/CS5 signal is transferred to MUX ST/CS pin
1
0
ST6/CS6 signal is transferred to MUX ST/CS pin
1
ST7/CS7 signal is transferred to MUX ST/CS pin
CS_MONITOR1, CS_MONITOR 0: select one out of the 4 different ChipSelectTimeouts,
served by CSN. The internal counter is reset by the rising edge of the CSN pin. When a
Timeout occurs the device enters FAIL SAFE mode (LimpHome).
CS_MONITOR1
CS_MONITOR0
0
max time for serving the CSN set to 50ms
0
1
max time for serving the CSN set to 100ms (default)
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