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參數(shù)資料
| 型號(hào)： | L98SI |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Octal Serial Solenoid Driver(八串行螺線管驅(qū)動(dòng)器) |
| 中文描述： | 八路系列電磁驅(qū)動(dòng)器（八串行螺線管驅(qū)動(dòng)器） |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大小： | 77K |
| 代理商： | L98SI |
TheL98SIDMOSoutputisalowoperatingpowerde-
vicefeatu-ring,eight 1
R
DSON
DMOSdrivers with
transient protection circuits in output stages. Each
channel is independently controlled by an output
latch anda commonRESET line which disablesall
eightoutputs.Thedriverhaslowsaturationandshort
circuitprotectionandcandriveinductiveandresistive
loads such as solenoids, lamps and relais. Data is
transmittedtothedeviceseriallyusingtheSerialPe-
ripheralInterface(SPI)protocol.Thecircuitreceives
8bitserialdatabymeansoftheserialinput(SI)which
is storedin an internal register to control the output
drivers. The serial output(SO) provides 8 bit of dia-
gnosticdatarepresentingthevoltagelevelatthedri-
ver output. This allows the microprocessor to
diagnosetheconditionof the outputdrivers.
The output saturation voltage is monitored by a
comparatorfor an outof saturationconditionandis
abletounlatchtheparticulardriverthroughthefault
resetline. This circuit is also cascadablewith ano-
ther octal driver in order to jam 8 bit multiple data.
The device is selected when the chip enable (CE)
lineis low.
Additionally the (SO) is placed in a tri-state mode
when the deviceis deselected.The negativeedge
of the(CE) transfersthe voltagelevel of thedrivers
totheshiftregisterandthepositiveedgeof the(CE)
latchesthenewdatafromtheshiftregistertothedri-
vers. When CE is Low, data bit contained into the
shift register is transferred to SO output at every
SCLKpositivetransitionwhile databitpresentatSI
inputislatchedintotheshiftregisteron everySCLK
negativetransition.
InternalBlocksDescription
The internal architectureof the deviceis based on
the threeinternalmajorblocks: the octalshiftregi-
sterfortalkingtothe SPIbus,theoctallatchforhol-
dingcontrolbitswrittenintothedeviceandthe octal
load driver array.
Shift Register
The shiftregisterhas bothserial andparallelinputs
and serial and parallel outputs.The serial inputac-
ceptsdatafromthe SPIbusandtheserial outputsi-
multaneously sends data into the SPI bus. The
paralleloutputsarelatchedinto theparallellatchin-
sidetheL98SIat theendof a datatransfer.Thepa-
rallelinputsjam diagnosticdataintotheshiftregister
at thebeginningof a datatransfercycle.
ParallelLatch
The parallellatchholds theinputdatafrom theshift
register.This datathen actuatestheoutputstages.
Individual registers in the latch may be cleared by
fault conditions in order to protect the overloaded
outputstages.Theentirelatchmayalsobecleared
by theRESET signal.
Output Stages
Theoutputstagesprovidean activelowdrivesignal
suitable for 0.75A continuous loads. Each output
has a currentlimit circuit whichlimits the maximum
outputcurrent to at least1.05Ato allowfor high in-
rushcurrents.Additionally,theoutputshaveinternal
zenersset to 36 voltsto clamp inductivetransients
at turn-off.Each output also has a voltagecompa-
ratorobservingtheoutputnode.If thevoltageexce-
eds 1.8V on an ON output pin, a fault condition is
assumedand the latch driving this particular stage
is reset,turningthe outputOFF to protectit. The ti-
ming of thisaction is describedbelow. Thesecom-
parators also provide diagnostic feedback data to
theshiftregister.Additionally,thecomparatorscon-
tainaninternalpulldowncurrentwhichwillcausethe
cell to indicate a low output voltageif the output is
programmedOFF andtheoutputpinisopencircui-
ted.
TIMINGDATA TRANSFER
Figure #2 showsthe overall timing diagram from a
byte transfer to and from the L98SI using the SPI
bus.
CE Highto Low Transition
TheactionbeginswhentheChipEnable(CE)pinis
pulledlow.Thetri-stateSerialOutput(SO)pindriver
willbe enabledentire timethatCE islow. Atthefal-
lingedgeof theCEpin,thediagnosticdatafromthe
voltagecomparatorsin theoutputstageswillbelat-
ched into the shift register. If a particular output is
high, a logic one will be jammed into that bit in the
shiftregister.Iftheoutputis low,a logiczerowillbe
loadedthere.Themostsignificantbit(07)shouldbe
presentedat theSerial Input (SI) pin. A zeroat this
pin will programan outputON, whilea onewill pro-
gramthe outputOFF.
SCLK Transitions
The Serial Clock (SCLK) pin shouldthenbe pulled
high.Atthispointthediagnosticbitfromthemostsi-
gnificantoutput(07)willappearat theSOpin.Ahigh
here indicates that the 07 pin is higher than 1.8V.
TheSCLKpinshouldthenbetoggledlowthenhigh.
NewSOdatawillappearfollowingeveryrisingedge
of SCLK and new SI data will be latched into the
L98SIshiftregisteronthefallingedges.Anunlimited
amount of data may be shifted through the device
FUNCTIONAL DESCRIPTION
L98SI
5/9
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