參數(shù)資料
型號： L9822N
廠商： 意法半導(dǎo)體
英文描述： OCTAL SERIAL SOLENOID DRIVER
中文描述： 八路串行電磁驅(qū)動
文件頁數(shù)： 5/9頁
文件大?。?/td> 87K
代理商： L9822N
TheL9822NDMOSoutputis alowoperatingpower
device featu-ring, eight 1
R
DSON
DMOS drivers
with transient protection circuits in output stages.
Eachchannelis independentlycontrolledbyan out-
putlatchanda commonRESETlinewhichdisables
all eight outputs.The driver has low saturationand
shortcircuitprotectionandcandriveinductiveandre-
sistive loads such as solenoids, lamps and relais.
DataistransmittedtothedeviceseriallyusingtheSe-
rialPeripheralInterface(SPI)protocol.Thecircuitre-
ceives 8 bit serial data by means of the serial input
(SI) which is stored in an internal register to control
theoutputdrivers.Theserialoutput(SO)provides8
bit of diagnosticdata representingthe voltage level
at the driver output.This allows the microprocessor
to diagnosethe conditionof theoutputdrivers.
The output saturation voltage is monitored by a
comparatorfor an outof saturationconditionandis
abletounlatchtheparticulardriverthroughthefault
resetline. This circuit is also cascadablewith ano-
ther octal driver in order to jam 8 bit multiple data.
The device is selected when the chip enable (CE)
lineis low.
Additionally the (SO) is placed in a tri-state mode
when the deviceis deselected.The negativeedge
of the(CE) transfersthe voltagelevel of thedrivers
totheshiftregisterandthepositiveedgeof the(CE)
latchesthenewdatafromtheshiftregistertothedri-
vers. When CE is Low, data bit contained into the
shift register is transferred to SO output at every
SCLKpositivetransitionwhile databitpresentatSI
inputislatchedintotheshiftregisteron everySCLK
negativetransition.
InternalBlocksDescription
The internal architectureof the deviceis based on
the threeinternalmajorblocks: the octalshiftregi-
sterfortalkingtothe SPIbus,theoctallatchforhol-
dingcontrolbitswrittenintothedeviceandthe octal
load driver array.
Shift Register
The shiftregisterhas bothserial andparallelinputs
and serial and parallel outputs.The serial inputac-
ceptsdatafromthe SPIbusandtheserial outputsi-
multaneously sends data into the SPI bus. The
paralleloutputsarelatchedinto theparallellatchin-
side the L9822Nat the end of a data transfer. The
parallelinputs jam diagnosticdata into the shiftre-
gisterat thebeginningof a datatransfercycle.
ParallelLatch
The parallellatchholds theinputdatafrom theshift
register.This datathen actuatestheoutputstages.
Individual registers in the latch may be cleared by
fault conditions in order to protect the overloaded
outputstages.Theentirelatchmayalsobecleared
by theRESET signal.
Output Stages
Theoutputstagesprovidean activelowdrivesignal
suitable for 0.75A continuous loads. The outputs
haveinternalzenerssetto 36 voltsto clamp induc-
tive transients at turn-off. Each output also has a
voltagecomparatorobservingtheoutputnode.Ifthe
voltageexceeds1.8V on an ON outputpin, a fault
conditionis assumedand the latchdriving this par-
ticularstageis reset,turningthe outputOFFtopro-
tect it. The timingof this action is describedbelow.
These comparators also provide diagnostic feed-
backdatatotheshiftregister.Additionally,thecom-
paratorscontainan internalpulldowncurrent which
will cause thecell to indicatea low outputvoltageif
the output is programmed OFF and the output pin
is opencircuited.
TIMINGDATA TRANSFER
Figure #2 showsthe overall timing diagram from a
byte transfer to and from the L9822NSPusing the
SPI bus.
CE Highto Low Transition
TheactionbeginswhentheChipEnable(CE)pinis
pulledlow.Thetri-stateSerialOutput(SO)pindriver
willbe enabledentire timethatCE islow. Atthefal-
lingedgeof theCEpin,thediagnosticdatafromthe
voltagecomparatorsin theoutputstageswillbelat-
ched into the shift register. If a particular output is
high, a logic one will be jammed into that bit in the
shiftregister.Iftheoutputis low,a logiczerowillbe
loadedthere.Themostsignificantbit(07)shouldbe
presentedat theSerial Input (SI) pin. A zeroat this
pin will programan outputON, whilea onewill pro-
gramthe outputOFF.
SCLK Transitions
The Serial Clock (SCLK) pin shouldthenbe pulled
high.Atthispointthediagnosticbitfromthemostsi-
gnificantoutput(07)willappearat theSOpin.Ahigh
here indicates that the 07 pin is higher than 1.8V.
TheSCLKpinshouldthenbetoggledlowthenhigh.
NewSOdatawillappearfollowingeveryrisingedge
of SCLK and new SI data will be latched into the
L9822N shift register on the falling edges.An unli-
mitedamountofdatamaybeshiftedthroughthede-
viceshiftregister(intotheSIpinandouttheSOpin),
allowingthe otherSPI devicesto be cascadedin a
daisy chainwiththe L9822N.
FUNCTIONAL DESCRIPTION
L9822N
5/9
相關(guān)PDF資料
PDF描述
L9823 Octal Low-Side Driver for bulb, resistive and inductive loads with serial input control, output protection and diagnostic
L9825 Octal Low-side Driver For Resistive and Inductive Loads With Serial / Parallel Input Control, Output Protection and Diagnostic
L9826 Octal Low-Side Driver for resistive and inductive loads with serial/parallel input control, output protection and diagnostic
L9830 MONOLITHIC LAMP DIMMER
L9848 OCTAL CONFIGURABLE LOW/HIGH SIDE DRIVER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
L9822N_03 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:OCTAL SERIAL SOLENOID DRIVER
L9822N013TR 功能描述:電源開關(guān) IC - 配電 OCTAL SOLENOID DRVR RoHS:否 制造商:Exar 輸出端數(shù)量:1 開啟電阻（最大值）:85 mOhms 開啟時間（最大值）:400 us 關(guān)閉時間（最大值）:20 us 工作電源電壓:3.2 V to 6.5 V 電源電流（最大值）: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOT-23-5
L9823 功能描述:電源開關(guān) IC - 配電 Octal Low Side RoHS:否 制造商:Exar 輸出端數(shù)量:1 開啟電阻（最大值）:85 mOhms 開啟時間（最大值）:400 us 關(guān)閉時間（最大值）:20 us 工作電源電壓:3.2 V to 6.5 V 電源電流（最大值）: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOT-23-5
L9823013TR 功能描述:電源開關(guān) IC - 配電 Octal Lowside Driver Bulb, Resistive RoHS:否 制造商:Exar 輸出端數(shù)量:1 開啟電阻（最大值）:85 mOhms 開啟時間（最大值）:400 us 關(guān)閉時間（最大值）:20 us 工作電源電壓:3.2 V to 6.5 V 電源電流（最大值）: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOT-23-5
L9824 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*