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參數(shù)資料
| 型號(hào)： | L9341V |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | QUAD LOW SIDE DRIVER |
| 中文描述： | 四路，低側(cè)驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 130K |
| 代理商： | L9341V |
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified: 8V
≤
V
S
≤
24V; 4.7V
≤
V
CC
≤
5.3V; –
40
°
C
≤
Tj
≤
150
°
C; I
O
≤
1A (note 3); I
O
≤
1.5A;V
sp
= V
S
for t
≤
400ms; V
OUTP
= V
OUT
for t
≤
400ms;
R
ext
= 12.4K
±
1%).
Symbol
I
ccq
I
sq
V
ccu
V
ccr
Parameter
Test Condition
Min.
Typ.
1
14
4
Max.
3
25
4.7
Unit
mA
mA
V
V
V
cc
Quiescent Current
V
s
Quiescent Current
V
cc
Undervoltage Threshold
V
cc
Range for RES1 and RES2
Operation
On Resistance
All Outputs Off
All Outputs Off
See Note 4
3
3
R
on
I
o
= 1A
T
j
= 125
°
C
T
j
= 25
°
C
750
450
m
m
I
o off
Off State Output Current
Outputs Off
1.4V
≤
V
o
≤
V
s
V
outp
= V
sp
= 40V
I
o
= 1A Output Off
T
j
= 25
°
C
T
j
= 125
°
C
I
o
= 1A Output Off
V
s
= 24V
V
sp
= 40V
V
sp
- V
o
= 40V
1
1
2.5
4
10
mA
mA
V
outf
Output Voltage During Flyback
V
s
+1.3
V
s
+1.1
V
V
I
gndf
Current to GND during Flyback
(see note 5)
17
20
44
52
500
mA
mA
μ
A
V
I
outr
V
inH
Reverse Leakage Current
High Input Level of SCLK,
SDI, CS, RES1, RES2
Low Input Level of SCLK,
SDI, CS, RES1, RES2
Hysteresis of Reset Inputs
RES1, RES2
Input Current on RES1,RES2
0.7*V
cc
V
cc
+0.3
V
inL
– 0.3
0.3*Vcc
V
V
REShys
0.3
1
V
I
inRESH
RES
i
= H; -2V
≤
V
sp
≤
8V
RES
i
= H; 8V
≤
V
sp
≤
40V
– 2V
≤
Vsp
≤
40V
I
SDO
= -1mA -2V
≤
V
sp
≤
40V
I
SDO
= 1mA -2V
≤
V
sp
≤
40V
0
≤
V
SDO
≤
V
cc
– 2V
≤
V
sp
≤
40V
– 10
5
– 10
0.9*V
cc
0
– 10
10
10
10
V
cc
0.4
10
μ
A
μ
A
μ
A
V
V
μ
A
I
in
Input Current on SCLK,SDI,CS
High Level SDO Output Voltage
Low Level SDO Output Voltage
SDO TristateHigh-Z Leakage
Current
PWM Duty Cycle
Frequency Accuracy Constant
Flyback Diagnostic Comparator
Threshold
Off State Diagnostic
Comparator Threshold
OutputCurrent Limitation Threshold
Delay Time PWM Signal to Out.
Output Voltage Rise andFall
Slope | du/dt |
Output Current Rise and Fall
Slope |di/dt|
V
SDOH
V
SDOL
I
SDOZ
PWM
duty
K
f
V
flyth
1/16
0.93*K
fn
V
s
– 1
1.5
1.5
15/16
1.07*K
fn
V
s
– 0.4
See Note 6
40
≥
V
sp
≥
8V
V
s
≤
8V
K
fn
V
V
V
V
offth
2
I
outl
t
dpo
S
ov
see Note 7
1.5
5
1.0
2.5
15
10
A
μ
s
V/
μ
s
(from 10 to 90% of V
o
) Fig. 2
S
oc
0.1
≤
Io
≤
1.5A
(from 10 to 90% of I
o
)
25
125
mA/
μ
s
Notes:
3.
The mean value is I
o
=1
T
∫
I
o
(
t
)
dt
0
T
;
4.
The outputs are switced off for Vcc
≤
Vccu. The logic is not reseted. For a reset,RES1 or RES2 mustbe used.
5.
This current is measured in the GND - terminalwhen one single output isin flyback and consists of the supply current added to the value
ofthe outputcurrent source and the leakage currentof the flyback diode. This leakage current is less than 1% of the nominal flyback current.
6.
The PWMfrequency is defined by an external capacitor. The PWMoscillator frequency is: f
pwm
=f
osc
32
withf
osc
=
K
f
C
1A/V and k
in
=15
10
-6
;
therange is: 300Hz
≤
f
≤
3000Hz. The OSC Pin can be alternatively driven by an external TTL / CMOS signal.
7. For I
out
≥
I
outl
an internalcomparator switches the corresponding output off for the currentPWM cycle.
L9341
3/10
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