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L8202
9
nRESET is an Output/Input signal (active low), that is used both to provide the information about the status
of Vcc and Vs supplies, both to provide a Reset signal to the internal logic when driven "low" from an ex-
ternal source for a period > 30
μ
s.
When nRESET is asserted, Motor Drivers and VDD regulator are forced in the inactive state and the Serial
Input Port is loaded with the "Reset Value".
To avoid false assertion due to glitches, nRESET is released to the "high" state with a delay of 100ms.
Delay period is calculated from the moment Vcc is passing the Vcc threshold.
At power down no delay is present, and nRESET is asserted low by Vcc or Vs falling low respect to their
thresholds
VOLTAGE SUPERVISOR
Figure 5.
Table 18. Electrical Characteristics
(T
j
= 25°C, V
S
= 32V, unless otherwise specified)
Table 19. Switching Characteristics
(T
j
= 25 °C, V
S
= 32V, unless otherwise specified)
Symbol
Vout_high
Parameter
Test Conditions
Ioh = -0.1 mA
Min.
Vcc-
0.5V
Typ.
Max.
Unit
V
High-level output voltage at
nRESET
Low-level output voltage at
nRESET
Vout_low
Vcc<
V
TH_VCC
Vs=38V
0.2
V
Rp_up
Internal pull-up resistance
between Vcc_in and nRESET
Threshold voltage at Vcc &
Vcc_in
2
3
5
K
V
TH_VCC
Vcc = 3.3V
Vcc_in = 3.3V
Vcc = 5.0V
Vcc_in = 3.3V
Vcc > VTH_VCC
Vs decreasing
Vcc > VTH_VCC
Vs increasing
( V
TH_Vs+
) -( V
TH_Vs-
)
2.87
2.82
4.35
2.87
18.0
3.07
3.10
4.65
3.10
20.0
V
V
TH_Vs-
Low threshold voltage at Vs
V
V
TH_Vs+
High threshold voltage at Vs
19.25
21.25
V
V
HYST_Vs
Hysteresis Voltage
1.2
V
Symbol
Td
Tdeglitch
Parameter
Test Conditions
Vcc >= V
TH_V
CC
nRESET deasserted
Vcc < V
TH_VCC
10 to 90%, 50pF Load
90 to 10%, 50pF Load
Min.
70
10
Typ.
100
20
Max.
130
30
Unit
ms
μ
s
nRESET delay
Vcc out of tolerance
persistence time
Rise Time at nRESET
Fall Time at nRESET
Trise
Tfall
750
50
ns
ns
Td
Td
Tdeglitch
Vs
Vcc
nRESET
V
TH_VCC
This should be less than Tdeglitch
A
Note A. L8202 ignores very brief transients.