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參數(shù)資料
| 型號(hào)： | L80223 |
| 英文描述： | L80223 10BASE-T/100BASE- TX/FX Ethernet PHY technical manual |
| 中文描述： | L80223 10BASE-T/100BASE-德克薩斯州/ FX以太網(wǎng)物理層技術(shù)手冊(cè) |
| 文件頁(yè)數(shù)： | 32/192頁(yè) |
| 文件大小： | 1306K |
| 代理商： | L80223 |
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Draft 6/5/00
2-12
Functional Description
Copyright 2000 by LSI Logic Corporation. All rights reserved.
The TX_CLK and RX_CLK clock frequency is reduced to 2.5 MHz
TX_ER is ignored
RX_ER is disabled and always held LOW
Receive operation is modified as follows:
On the receive side, when the squelch circuit determines that invalid
data is present on the TP inputs, the receiver is idle. During idle,
RX_CLK follows TX_CLK, RXD[3:0] is held LOW, and CRS and
RX_DV are deasserted. When a start of packet is detected on the
TP receive inputs, CRS is asserted and the clock recovery process
starts on the incoming TP input data. After the receive clock has
been recovered from the data, the RX_CLK is switched over to the
recovered clock and the data valid signal RX_DV is asserted on a
falling edge of RX_CLK. Once RX_DV is asserted, valid data is
clocked out on RXD[3:0] on the falling edge of RX_CLK. The
RXD[3:0] data has the same packet structure as the TXD[3:0] data
and is formatted on RXD[3:0] as specified in IEEE 802.3 and shown
in
Figure 2.3
. When the end of packet is detected, CRS and RX_DV
are deasserted. CRS and RX_DV also stay deasserted as long as
the device is in the Link Fail State.
2.2.2.2 FBI Interface
The Five Bit Interface (also referred to as FBI) is a five-bit wide interface
that is produced when the 4B5B encoder/decoder is bypassed. The FBI
is primarily used for repeaters or Ethernet controllers that have integrated
encoder/decoders.
The FBI is identical to the MII except:
The FBI data path is five bits wide, not nibble wide like the MII
The TX_ER pin is reconfigured to be the fifth transmit data bit
(TXD4)
The RX_ER pin is reconfigured to be the fifth receive data bit (RXD4)
CRS is asserted as long as the device is in the Link Pass State
COL is not valid
RX_DV is not valid
The TX_EN pin is ignored
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| L80225 | L80225 10/100 MbpsTX/10BT Ethernet Physical Layer Device (PHY) technical manual 4/02 |
| L80223 | 10BASE-T/100BASE-TX/FX Ethernet Physical Layer Device (PHY)(10BASE-T/100BASE-TX/FX 以太網(wǎng)物理層處理器) |
| L80600 | L80600 10/100/1000 Mbits/s Ethernet PHY technical manual 3/01 |
| L811-1X1T-03 | 1port.None LEDs.low profile RJ45 10/100Base-TX |
| L82-510 | Logic IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| L80223/A | 制造商:LSI Corporation 功能描述:PN may be NE DW |
| L80223/C | 制造商:LSI Corporation 功能描述:PN may be NE DW |
| L80223/D | 制造商:LSI Corporation 功能描述:PHY 1-CH 10Mbps/100Mbps 64-Pin LQFP |
| L80223/D-E6 | 制造商:LSI Corporation 功能描述:TRANSITION TO P/N 68032B1 - Bulk |
| L80223/D-LEADFREE | 制造商:LSI Corporation 功能描述: |
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