參數(shù)資料
型號(hào): L6917DTR
英文描述: Analog IC
中文描述: 模擬IC
文件頁(yè)數(shù): 7/27頁(yè)
文件大?。?/td> 411K
代理商: L6917DTR
7/27
L6917
15
PGNDS2
Channel 2 PowerGround sense pin. The net connecting the pin to the sense (Through a resistor
R
g
) point must be routed as close as possible to the ISEN2 net in order to couple in common
mode any picked-up noise.
16
ISEN2
Channel 2 current sense pin. The output current may be sensed across a sense resistor or
across the low-side mosfet Rds
ON.
This pin has to be connected to the low-side mosfet drain or
to the sense resistor through a resistor Rg in order to program the positive current limit at 140%
as follow:
Where 35
μ
A is the current offset information relative to the Over Current condition (offset at OC
threshold minus offset at zero load).
In the same way the negative current limit threshold results to be set at –50% as follow
Where –12.5
μ
A is the current offset information relative to the Negative Over Current condition
(offset at Negative OC threshold minus offset at zero load).
The net connecting the pin to the sense point must be routed as close as possible to the
PGNDS2 net in order to couple in common mode any picked-up noise.
17
OSC/INH
FAULT
Oscillator switching frequency pin. Connecting an external resistor from this pin to GND, the
external frequency is increased according to the equation:
Connecting a resistor from this pin to Vcc (12V), the switching frequency is reduced according to
the equation:
If the pin is not connected, the switching frequency is 300KHz.
Forcing the pin to a voltage lower than 0.8V, the device stop operation and enter the inhibit state.
The pin is forced high when an over voltage is detected and after three hiccup cycles. This
condition is latched; to recover it is necessary turn off and on VCC.
18-22
VID4-0
Voltage IDentification pins. These input are internally pulled-up and TTL compatible. They are
used to program the output voltage as specified in Table 1 and to set the power good thresholds.
Connect to GND to program a ‘0’ while leave floating to program a ‘1’.
23
PGOOD
This pin is an open collector output and is pulled low if the output voltage is not within the above
specified thresholds.
If not used may be left floating.
24
BOOT2
Channel 2 bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper
mosfet. Connect through a capacitor to the PHASE2 pin and through a diode to Vcc (cathode vs.
boot).
25
UGATE2 Channel 2 high side gate driver output.
26
PHASE2
This pin is connected to the source of the upper mosfet and provides the return path for the high
side driver of channel 2.
27
LGATE2
Channel 2 low side gate driver output.
28
PGND
Power ground pin. This pin is common to both sections and it must be connected through the
closest path to the low side mosfets source pins in order to reduce the noise injection into the
device.
PIN FUNCTION
(continued)
N
Name
Description
I
MAX_POS2
35
μ
A R
g
sense
--------------------------
=
I
MAX_NEG2
12.5
μ
sense
----------------------------------
A R
g
=
f
S
300KHz
6
OSC
)
-----------------------------
+
=
f
S
300KHz
7
OSC
)
-----------------------------
+
=
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