參數(shù)資料
型號: L6740L
廠商: 意法半導(dǎo)體
英文描述: Hybrid controller (4+1) for AMD SVID and PVID processors
中文描述: 混合控制器(4 1對AMD SVID和PVID)處理器
文件頁數(shù): 19/44頁
文件大?。?/td> 657K
代理商: L6740L
L6740L
Hybrid CPU support and CPU_TYPE detection
19/44
transition for the addressed section(s) or, more in general, react to the sent command
accordingly. Refer to
Figure 7
,
Table 8
and
Table 9
for details about the
Set VID Command.
L6740L is able to manage individual power OFF for both the Sections. The CPU may issue
a serial VID command to power OFF or power ON one Section while the other one remains
powered. In this case, the PWRGOOD signal remains asserted.
Figure 7.
SVI communications - Send byte
Table 8.
SVI send byte - Address and data phase description
bits
Description
Address phase
6:4
Always 110b.
3
Not Applicable, ignored.
2
Not Applicable, ignored.
1
CORE Section
(1)
.
If set then the following data byte contains the VID code for CORE Section.
1.
Assertion in both bit 1 and 0 will address the VID code to both CORE and NB simultaneously.
0
NB Section
(1)
.
If set then the following data byte contains the VID code for NB Section.
Data phase
7
PSI_L Flag (Active low).When asserted, the VR is allowed to enter Power-Saving
mode. See
Section 5.4.3
.
6:0
VID Code. See
Table 9
.
SVC
SVD
START
110b
ACK
ACK
Slave Addressing
(7 Clocks)
6
5
4
0
WRITE
(1Ck)
ACK
(1Ck)
7
6
0
3
Data Phase
(8 Clocks)
ACK
(1Ck)
STOP
START
SLAVE ADDRESSING + W
ACK
DATA PHASE
ACK
STOP
BUS DRIVEN BY L6740L
BUS DRIVEN BY MASTER (CPU)
相關(guān)PDF資料
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L6740LTR Hybrid controller (4+1) for AMD SVID and PVID processors
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