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參數資料
| 型號： | L6714 |
| 廠商： | 意法半導體 |
| 英文描述： | 4 phase controller with embedded drivers for Intel VR10, VR11 and AMD 6Bit CPUs |
| 中文描述： | 4英特爾VR10，VR11和AMD的6位嵌入式CPU的司機相控制器 |
| 文件頁數： | 10/70頁 |
| 文件大?。?/td> | 572K |
| 代理商： | L6714 |
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Pin settings
L6714
10/70
33
OVP
Over Voltage Programming Pin. Internally pulled up by 12.5μA(typ) to 5V.
Set free to use built-in protection thresholds as reported into
Table 10
.
Connect to SGND through a R
OVP
resistor and filter with 100pF (max) to set the
OVP threshold to a fixed voltage according to the R
OVP
resistor.
See “Over voltage and programmable OVP” Section
Section for details.
34
VID_SEL
Intel Mode.
It allows selecting between VR10 (short to SGND,
Table 7
) or VR11
(floating,
Table 6
) DACs ,internally pulled up by 12.5
μ
A (typ.)..
See “Configuring
the device” Section
for details.
AMD Mode.
Not Applicable. Needs to be shorted to SGND.
35
FBR
Remote Buffer Non Inverting Input.
Connect to the positive side of the load to perform remote sense.
See “Layout guidelines” Section
for proper layout of this connection.
36
FBG
Remote Buffer Inverting Input.
Connect to the negative side of the load to perform remote sense.
See “Layout guidelines” Section
for proper layout of this connection.
37
OSC/
FAULT
Oscillator Pin.
It allows programming the switching frequency F
SW
of each channel: the
equivalent switching frequency at the load side results in being multiplied by the
phase number N.
Frequency is programmed according to the resistor connected from the pin vs.
SGND or VCC with a gain of 6kHz/μA (see relevant section for details). Leaving
the pin floating programs a switching frequency of 150kHz per phase.
The pin is forced high (5V) to signal an OVP FAULT: to recover from this
condition, cycle VCC or the OUTEN pin.
See “Oscillator” Section
for details.
38
VID7/
DVID
VID7 - Intel Mode.
See VID5 to VID0 Section.
DVID - AMD Mode.
DVID Output.
CMOS output pulled high when the controller is performing a D-VID transition
(with 32 clock cycle delay after the transition has finished).
See “Dynamic VID
transitions” Section
Section for details.
39
VID6
Intel Mode.
See VID5 to VID0 Section.
AMD Mode.
Not Applicable. Need to be shorted to SGND.
40 to
45
VID5 to
VID0
Intel Mode.
Voltage IDentification Pins (also applies to VID6, VID7).
Internally pulled up by 25μA to 5V, connect to SGND to program a '0' or leave
floating to program a '1'.
They allow programming output voltage as specified in
Table 6
and
Table 7
according to VID_SEL status. OVP and UVP protection comes as a
consequence of the programmed code (
See Table 10
).
AMD Mode.
Voltage IDentification Pins.
Internally pulled down by 12.5μA, leave floating to program a '0' while pull up to
more than 1.4V to program a '1'.
They allow programming the output voltage as specified in
Table 9 on page 21
(VID7 doesn’t care). OVP and UVP protection comes as a consequence of the
programmed code (
See Table 10
).
Note.
VID6 not used, need to be shorted to SGND.
Table 1.
Pin functions
N°
Pin
Function
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