
FUNCTIONAL DESCRIPTION
Inside the system is the sensorless Spindle driver
(Spin), the Voice Coil Motor driver (VCM), the
Head load/unload predrivers, power sequencing,
actuator over-velocity detection, actuator retrac-
tion and dynamic braking. The architecture of the
system is configured to interface directly to an 8
bit, parallel, microprocessor bus.
During the application of power to the system
(power-on), the output drivers are held in a disabled
state until the applied voltage reaches the Voltage
Good Threshold (VGT). During this period of time
the output drivers are disabled, the internal register
are set to predetermined states, and the Power On
Reset (POR) signal is held low. The POR signal is
held low from the time the applied voltage
reaches 0.7V and the VGT. The POR delay is
programmable changing the value of a capacitor.
The VCM driver is driven via a D/A and it can be
enabled through the VCM driver register. The
VCM driver has a gain capability too. This func-
tion is to be accomplished by switching the sense
resistor used such that the current sensing feed-
back in the VCM driver has more information and
therefore results in lower deadband, offset cur-
rent, and gain error. An actuator over velocity
sensing circuit is incorporated in the system,
which is accomplished by measuring BEMF volt-
age and comparing to a threshold.
ELECTRICAL CHARACTERISTICS (Continued)
Step-up converter
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Units
VSU
Step-up Voltage
Relative to VCC
711
V
Microprocessor interface (Note 10)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Units
VIH
High Level Input Voltage
3
V
VIL
Low Level Input Voltage
0.8
V
VOH
High Level Output Voltage
VCC = 5V, IOH = 400
A
4.4
V
VOL1
Low Level Output Voltage
–MCERR, –POR, –DTACK
IOL = 4mA
0.4
V
VOL2
Low Level Output Voltage
SYNT_ALL
IOL = 0.5mA
0.4
V
IIN1
Input Leakage Current
–RD, –WR, AS, –MC_CS,
SYSCLK, A [0:2]
1
A
IIN2
Input Leakage Current
D [0:7]
10
A
Microprocessor interface timing
Trddh
Read Data Hold
5
40
ns
Trddt
–RD High to –DTACK high
40
ns
Twrdt
–WR High to –DTACK High
40
ns
Power on reset
VCCHL
VCC Good, HL
VCC falling
4.2
4.4
V
VCCHL
VCC Good, LH
VCC rising
4.26
4.5
V
TPLH
Rise Time
CLoad = 100pF
200
ns
RT
Response Time
50
s
Notes:
1) The minimum voltage available from the brushless DC motor after power has been removed is 2.7V
2) The voltage available for actuator etraction shall be greater than 0.7V.
3) Sum of Ibias+(Vref/internal resistor + power leakage).
4) Minimum output voltage is set to Vref by a resistor network.
5) The VCM DAC shall be monotonic over its full range.
6) The coding of the digital input shall be 2’s complement.
7) The voltage available for solenoid operation shall be greater than 1.9V.
8) The Spin DAC shall be monotonic over its full range.
9) The coding of the digital input shall be uniplar (unsigned binary).
10) SYNTH_HALL, MC_ERR, DTACK and POR shall have open drain (collector) outputs and internal pull-up resistors. The minimum value of
these pull-up resistors shall be 20K
..
L6245
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