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參數(shù)資料
| 型號： | L6181ADIP28 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | OCTAL LINE RECEIVER |
| 中文描述： | 八進制線路接收器 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 157K |
| 代理商： | L6181ADIP28 |
ELECTRICALCHARACTERISTICS
(V
CC
= 5V
±
5%; V
CM
= -7 to 7V; Tamb = 0 to 70
°
C;
V
SS
= -9 to 13.5V; V
DD
= 9 to 13.5V; unless otherwisespecified.)
Symbol
f
R
Parameter
Test Condition
Min.
Typ.
5
Max.
Unit
MHz
Frequency Rejected
(No Receiver Output)
V
IN
= 2Vpp;
(see fig. 8 and note 7)
Note:
1) The algebric convention, wherethe less positive (more negative) is designedthe minimum
2) With the voltage V
IA
or (V
IB
) ranging between
±
15V, while V
IB
or (V
IA
) is open or grounded, the resultant input current I
IA
or (I
IB
) shallremain
within the shaded region shown inthe graph in Fig.1.
3) Either Point B’ or Point A’ is grounded in Figure 1
4) V
ICC
measured from grounded to (+) input with (-) input grounded
V
ICC
measured from grounded to (+) input with (-) input grounded
5) Not more than oneoutput should be shorted at a time and forless than 1 seond
6) The sum of the product of the maximum supply currents and voltages cannot exceed themaximum power dissipation
7)
A: The conditions for the inpit switching from V
IOCL
to V
IOCH
mode is: V
id
in startbit ”spacing condition”for less thanTpV
ioch
(5ms).
B: The conditions for the input switching from V
IOCH
to V
IOCL
mode is: Vid> W
W2
for greater than TpV
IOCL
(200ms)
8)
An example of a frequencyresponse plot meeting the rejection/acceptance requirements is provided in figure8.
LINE TRANSIENT IMMUNITY
(Considering the following cases; powered ON, Powered OFF-LOW im-
pedancepower supplyand poweredOFF-HIGH impedancesupply)
Symbol
ESD
Parameter
Test Condition
Min.
2
Typ.
Max.
Unit
KV
Static
tested per MIL-STD-883
(see note 9)
transient pulse bothpolarities
for 100
μ
s (seenote9 and Fig. 2)
EOS
Stress
50
V
Note:
9) Allpins are required to withstand this parameters.
10) Input pins are required to withstand fig.2 without any degradation tothe circuit.
11) The balance test requirement can be met by use of a currentlimit circuit which reduces the input bias current I
ib
(see figure7)
for input voltages below a threshold voltage given by (I
ib
x 1K)- 400mV.
Figure1:
Input Current VoltageMesurements
L6180 - L6181
4/10
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