參數(shù)資料
型號: L5993D
廠商: 意法半導(dǎo)體
英文描述: CONSTANT POWER CONTROLLER
中文描述: 恒功率控制器
文件頁數(shù): 9/22頁
文件大?。?/td> 200K
代理商: L5993D
ered at pin 1 and definesthe upperextreme of the
duty cycle range, D
x
(see pin 15 for D
x
definition
and calculation).
In case V
15
is connectedto VREF, however, the
switching frequency of the system will be a half
f
osc
.
If the IC is to be synchronizedto an externaloscil-
lator, R
T
and C
T
should be selected for a f
osc
lower than the master frequency in any condition
(typically, 10-20% ), depending on the tolerance
of R
T
and C
T
.
Pin 3.
DC (Duty Cycle Control). By biasing this
pin with a voltagebetween1 and 3 V it is possible
to set the maximumduty cycle between 0 and the
upper extremeD
x
(see pin 15).
If D
max
is the desired maximum duty cycle, the
voltageV3 to be appliedto pin 3 is:
V
3
= 5 - 2
(2-Dmax)
(4)
D
max
is determined by internal comparison be-
tween V3 and the oscillator ramp (see fig. 22),
thus in case the device is synchronized to an ex-
ternal frequency f
ext
(and therefore the oscillator
amplitudeis reduced),(4) changes into:
V
3
=
5
4
exp
A voltage below 1V will inhibit the driver output
stage. This could be used for a not-latcheddevice
disable, for example in case of overvoltage pro-
tection(see applicationideas).
If no limitation on the maximum duty cycle is re-
D
max
R
T
C
T
f
ext
(5)
quired (i.e. D
MAX
= D
X
), the pin has to be leftfloat-
ing. An internal pull-up (see fig. 22) holds the volt-
age above 3V. Should the pin pick up noise (e.g.
during ESD tests), it can be connected to VREF
througha 4.7k
resistor.
Pin 4.
VREF (Reference Voltage). The device is
provided with an accurate voltage reference
(5V
±
1.5%) able to deliver some mA to an external
circuit.
A small film capacitor (0.1
μ
F typ.), connected
between this pin and SGND, is recommended to
ensure the stability of the generator and to prevent
noisefrom affectingthereference.
Before device turn-on, this pin has a sink current
capabilityof 0.5mA.
+
-
R2
R3
R1
CLAMP
D1
50
R
T
C
T
D
R
Q
600
μ
A
D97IN500B
V
REF
RCT
SYNC
CLK
2
4
1
Figure 21. Oscillatorand synchronization internalschematic.
+
-
R2
R1
R
T
C
T
D97IN711A
V
REF
RCT
DC
TO PWM LOGIC
4
3
2
23K
28K
3
μ
A
Figure22. Duty cycle control.
L5993
9/22
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