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參數(shù)資料
| 型號(hào)： | L5993D013TR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1.5 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | SO-16 |
| 文件頁(yè)數(shù)： | 4/22頁(yè) |
| 文件大?。?/td> | 200K |
| 代理商： | L5993D013TR |
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Pin 12. SGND (Signal Ground). This ground refer-
ences the control circuitry of the IC, so all the
ground connections of the external parts related
to control functions must lead to this pin. In laying
out the PCB, care must be taken in preventing
switched high currents from flowing through the
SGND path.
Pin 13. ISEN (Current Sense). This pin is to be
connected to the ”hot” lead of the current sense
resistor Rsense (being the other one grounded), to
get a voltage ramp which is an image of the cur-
rent of the switch (IQ). When this voltage is equal
to:
V13pk = IQpk Rsense =
VCOMP
1.4
3
(8)
the conduction of the switch is terminated.
To increase the noise immunity, a ”Leading Edge
Blanking” of about 100ns is internally realized as
shown in fig. 27. Because of that, the smoothing
RC filter between this pin and Rsense could be re-
moved or, at least, considerably reduced.
Pin 14. DIS (Device Disable). When the voltage
on pin 14 rises above 2.5V the IC is shut down
and it is necessary to pull VCC (IC supply voltage,
pin 8) below the UVLO threshold to allow the de-
vice to restart.
The pin can be driven by an external logic signal
in case of power management, as shown in fig.
28. It is also possible to realize an overvoltage
protection, as shown in the section ” Application
Ideas”.If used, bypass this pin to ground with a fil-
ter capacitor to avoid spurious activation due to
noise spikes. If not, it must be connected to
SGND.
Pin 15. DC-LIM (Maximum Duty Cycle Limit). The
upper extreme, Dx, of the duty cycle range de-
pends on the voltage applied to this pin. Approxi-
mately,
Dx
RT
+ 230
(9
)
if DC-LIM is grounded or left floating. Instead,
connecting DC-LIM to VREF (half duty cycle op-
tion), Dx will be set approximately to:
Dx
RT
2
RT + 260
(10)
and the output switching frequency will be halved
with respect to the oscillator one because an in-
ternal T flip-flop (see block diagram, fig. 1) is acti-
vated. Fig. 29 shows the operation.
The half duty cycle option speeds up the dis-
charge of the timing capacitor CT (in order to get
duty cycles as close as possible to 50%) so the
oscillator frequency - with the same RT and CT -
will be slightly higher.
The halving of frequency can be used to reduce
losses at light load in all those systems that must
comply with requirements regarding energy con-
sumption (e.g. monitor displays, see ”Application
Ideas”).
+
-
I
D97IN503
ISEN
0
3V
CLK
2V
+
-
+
-
1.2V
FROM E/A
OVERCURRENT
COMPARATOR
PWM
COMPARATOR
TO PWM
LOGIC
TO FAULT
LOGIC
13
Figure 27. Internal LEB.
+
-
C
D97IN502
DIS
D
R
Q
DISABLE
UVLO
2.5V
14
DISABLE
SIGNAL
Figure 28. Disable (Latched)
L5993
12/22
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