參數(shù)資料
型號: L5991D
廠商: STMICROELECTRONICS
元件分類: 穩(wěn)壓器
英文描述: 1.5 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16
封裝: SO-16
文件頁數(shù): 23/23頁
文件大?。?/td> 414K
代理商: L5991D
The oscillation frequency can be established with
the aid of the diagrams of fig. 14, where RT will be
intended as the parallel of RA and RB in normal
operation and RT = RA in standby, or considering
the following approximate relationships:
fosc
1
CT
(0.693 (RA // RB) + KT
(1),
which gives the normal operating frequency, and:
fSB
1
CT
(0.693 RA + KT
)
(2),
which gives the standby frequency, that is the one
the converter will operate at when lightly loaded.
In the above expressions, RA // RB means:
RA//RB
=
RA
RB
RA
+ RB
,
while KT is defined as:
KT
=
90 V15
= VREF
160 V15
= GND/OPEN
(3),
and is related to the duration of the falling-edge of
the sawtooth:
Td
30 109 + KT
CT (4).
Td is also the duration of the sync pulses deliv-
ered at pin 1 and defines the upper extreme of the
duty cycle range, Dx (see pin 15 for DX definition
and calculation) since the output is held low dur-
ing the falling edge.
In case V15 is connected to VREF, however, the
switching frequency will be a half the values taken
from fig. 14 or resulting from (1) and (2).
To prevent the oscillator frequency from switching
back and forth from fosc to fSB, the ratio fosc / fSB
must not exceed 5.5.
If during normal operation the IC is to be synchro-
nized to an external oscillator, RA, RB and CT
should be selected for a fosc lower than the master
frequency in any condition (typically, 10-20% ),
depending also on the tolerance of the parts.
Pin 3. DC (Duty Cycle Control). By biasing this
pin with a voltage between 1 and 3 V it is possible
to set the maximum duty cycle between 0 and the
upper extreme Dx (see pin 15).
If Dmax is the desired maximum duty cycle, the
voltage V3 to be applied to pin 3 is:
V3 = 5 - 2
(2-Dmax)
(5)
Dmax is determined by internal comparison be-
tween V3 and the oscillator ramp (see fig. 24),
thus in case the device is synchronized to an ex-
ternal frequency fext (and therefore the oscillator
amplitude is reduced), (5) changes into:
V3
= 5 4 exp
Dmax
RT
CT fext
(6)
A voltage below 1V will inhibit the driver output
stage. This could be used for a not-latched device
disable, for example in case of overvoltage pro-
tection (see application ideas).
If no limitation on the maximum duty cycle is re-
quired (i.e. DMAX = DX), the pin has to be left float-
ing. An internal pull-up (see fig. 24) holds the volt-
age above 3V. Should the pin pick up noise (e.g.
+
-
R2
R3
R1
CLAMP
D1
50
RA
CT
D
R
Q
600
A
D97IN729A
VREF
RCT
SYNC
CLK
2
4
1
16
ST-BY
RB
STANDBY
Figure 23. Oscillator and synchronization internal schematic.
L5991 - L5991A
9/23
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