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參數(shù)資料
| 型號： | L4990A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | PRIMARY CONTROLLER |
| 中文描述： | 主控制器 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 322K |
| 代理商： | L4990A |
referenced to 1.2V detects primary over-current
conditions. On detection of an overcurrent fault
the output is immediately shutdown and the fault
is also latched. A Fault Reset Delay is imple-
mented by discharging the external Soft Start
(SS) timing capacitor
before resetting the fault
latch and initiating a softstartcycle.
In case of a continuous fault condition the SS ca-
pacitor is charged to 5V before being discharged
again, to ensure that the fault frequency does not
exceed the programmedsoft start frequency.
Duty CycleLimit
A simpleconnectionbetween the DC-LIMand the
available Vref activatesan internal T- FlipFlop lim-
iting the DC to about 50%. If this pin is not con-
nected or grounded, the limit of the duty cycle is
extended to about100%
Duty CycleControl
Duty Cycle DC is externally programmed by set-
ting a voltage between 1V (0% DC) and 3V
(100% DC) at the DC pin. The programmed volt-
age is compared with the oscillator C
T
capacitor
charging waveform to determine the maximum
ON-time in each period. This function gives a fine
control of DC.
If this pin is floating the maximum duty cycle de-
pends on DC-LIM status.
Synchronization
A SYNC pin eases Synchronization of the IC to
the external world ( e.g.
another IC working in
parallelor to TV/monitorsync signal).
In TV/monitor applications the timing components
R
T
, C
T
are set for a frequency lower than the
minimum TV sync frequency.When the TV circuit
has powered-up it takes over and the system fre-
quencyis that of the SYNC. Duty Cycle is control-
lable using the DC function.
In parallel operation of several IC’s no Mas-
ter/Slavedesignationis requiredas the higherfre-
quency IC is automatically the master. Controllers
to be synchronized have their SYNC pins tied to-
gether and each SYNC pin operatesas a bidirec-
tional circuit. The first IC to drive its SYNC pin is
the master and it initiates a discharge of the C
T
timing capacitor of every controller. The Sync in-
put signal is edge-triggered and sets an internal
”sync latch” which ensures full discharge of C
T
.
DisableFunction
The DIS pin performs a logic level latched-shut-
down function. When pulled above 2.5V it shuts
down the complete IC with a standby current of
<270
μ
A (typ).
To reset the IC the V
CC
pin must be pulled-down
below the lower UVLO threshold (10V).
LeadingEdge Blanking(LEB)
An LEB interval of 100ns has been incorporated
into the IC to blank out the current sense signal
during the first 100nsfrom switch turn-on.
This provides noise immunity to turn-on spikes
and reducesexternal RC filteringrequirements on
the current-sensesignal.
6
8
20
30
V14 = 0, OSC=disabled
T j = 25
°
C
0
4
8
12
16
20
24
0
0.2
0.4
0.6
0.8
1
Vcc [V]
Iq [mA]
X
Y
Figure 1. Quiescentcurrent vs. input voltage.
(X = 7.6V and Y = 8.4V for L4990A)
8
10
12
14
16
18
20
22
24
210
240
270
300
Vcc
[V]
Iq
[uA]
V14 = Vref
Tj = 25
°
C
Figure2. Quiescentcurrent vs. input voltage
(after disable).
L4990 - L4990A
5/24
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