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參數(shù)資料
| 型號(hào)： | L4985 |
| 文件頁數(shù)： | 18/23頁 |
| 文件大?。?/td> | 415K |
| 代理商： | L4985 |
APPLICATION HINTS
Oscillator(pin18)
An external capacitor, Cosc, connected between
pin 18 and SGND fixes the oscillator frequency
fsw. In the range from 25 kHz to 350 kHz, fsw is
given by:
fsw = 31 - 8
Cosc + 32/Cosc,
[fsw]=kHz, [Cosc]=nF
A value of 85 kHz (Cosc = 560 pF) is suggested
as optimum trade-off between high efficiency and
output filter size reduction.
Comp (pin13)
An E/A compensation networks providing two
pole-zero pairs is suggested for stabilizing the
control loop of the L4985. In fig. 38, an example
of such a kind of network is shown. In fig. 39 the
bode plot of its gain is drawn.
Power Management (pins 2& 3)
Pin 3 (DIS1), controls the enabling/disabling of
the whole chip. A low level (below 0.9V) disables
it, reducing the current absorbed from the supply
to few A (sleep mode). A voltage above 3V en-
ables the chip operation.
Pin 2 (DIS2) works just like DIS1 but controls the
auxiliary converter only, leaving the main con-
verter still operating.
Internal Boost (pins 7 & 8)
This low power converter is used to generate a
DCbus, delivering 10 V above the supplyvoltage,
needed for driving the internal NDMOS switches.
This solution does not put any limitation both to
maximum duty cycle and to minimum load cur-
rent.
The internal boost uses, as external components,
a small chip or axial inductor (connected to the
V
S
) and a capacitor(connectedto PWGND).
The inductance should be in the range 100 to 200
μ
H, with few ohms of seriesresistance to limit the
peak current.
The capacitor will be an electrolytic one (10 uF is
OK) withoutany particular requirement.
Gate Driver (pin9)
This output can drive an external PowerMOS act-
ing as a synchronousrectifier for achieving maxi-
mum efficiencyat high load current.
The driver can deliver up to 30 nC per cycle with
a 10 V voltage, and that must be taken into ac-
count when selecting the external PowerMOS,
becauseof its gate charge.
A small Schottky diode in parallel to the external
PowerMOS is still used in order to avoid power
losses due to the turn-on of the PowerMOSinher-
entdiode.
Reset Function (pins 1 & 20)
The RESET signal, delivered at pin 1 with an
open drain output (compatible to V
S
), indicates
with a low level either that the chip is disabled or
that an outputvoltage drop has occurred.
The high level appears,after a programmablede-
lay, as the chip is enabled or the ouptut voltage
has recovered its correct value.
Figure38:
E/A CompensationNetwork
Figure39:
E/A CompensationNetwork Gain.
L4985
18/23
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參數(shù)描述 |
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| L4987CPT30 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:VERY LOW DROP VOLTAGE REGULATORS WITH INHIBIT AND DROPOUT CONTROL FLAG |
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