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參數(shù)資料
| 型號： | L3235N |
| 英文描述： | HIGHLY INTEGRATED SLIC KIT TARGETED TO PABX AND KEY SYSTEM APPLICATIONS |
| 中文描述： | 高度集成的用戶接口盒針對交換機與關(guān)鍵系統(tǒng)應(yīng)用 |
| 文件頁數(shù)： | 11/25頁 |
| 文件大?。?/td> | 3164K |
| 代理商： | L3235N |
THERMAL DATA
Symbol
R
th j-amb
Description
Value
60
Unit
°
C/W
Thermal Resistance Junction-ambient
Max
PIN DESCRIPTION
N°
Name
Description
1,4,5,8,
15,16,19
,21,23,
26,30,33
,36,37,
41,42
NC
Not Connected
2
AGND
Analog/Digital Ground.
3
BGND
Battery Ground. This is the Reference for the Battery Voltage (note 1).
6
CAC
AC Current Feedback Input.
7
RPC
External Protection Resistors AC Transmission Compensation.
9
TX
Four Wire Transmitting Amplifier Output.
10
ZB
Non Inverting Operational Input Inserted in the Hybrid Circuit for 2W to 4W Conversion.
The Network Connected from this Pin to Ground shall be a copy of the Line Impedance.
11
ZA
VRX Output Buffer 2W to 4W Conversion.
12
RX
High Impedance Four Wire Receiving Input.
13
V
CC
Positive 5V Supply Voltage.
14
REF
Voltage Reference Output; a Resistor Connected to this pin sets the Internal Bias Current.
17
V
SS
Negative 5V Supply Voltage.
18
IL
Transversal Line Current Feedback Divided by 50.
20
VPOL
Non Inverting Operational Input to Implement DC Character.
22
BASE
Driver for External Transistor Base.
24
LIM
Voltage Reference Output; a Resistor Connected to this Pin Sets the Value of Line
Current Limitation.
25
RNG
Ringing Logic Input from Line Card Controller.
27
SBY
Stand by Logic Input (SBY = 1 Set Line Current Limitation at 3mA).
28
PU
Power u.p Logic Output for the Codec Filter. (PU = 0 means Codec Filter Activated)
29
CS
Ring Injector Enable for L3234 Output. (CS = 1 means L3234 Ringing Injection Enable).
31
OH
Hook Status Logic Output (OH = 0 means off hook).
32
GDK
Ground Key Status Logic Output (GDK = 0 means Ground Key on).
34
RTF
Time Constant Hook Detector Filter Input.
35
GKF
Time Constant GK Detector Filter Input.
38
TIP
Tip Wire of 2 Wire Line Interface.
39
V
bat
Negative Battery Supply Input.
40
RING
RING wire of 2 Wire Line Interface.
43
ZAC
Non Inverting Input of the AC Impedance Synthesis Circuit.
44
VREG
Emitter Connection for the External Transistor.
Note 1:
AGND and BGND pins must be tied together at a low impedance point (e.g. at card connector level).
L3234 - L3235N
11/25
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