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參數(shù)資料
| 型號： | KXPC8255CZUIFBC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 3/41頁 |
| 文件大小： | 0K |
| 描述： | IC MPU POWERQUICC II 480-TBGA |
| 標準包裝： | 2 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 200MHz |
| 電壓： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 480-LBGA |
| 供應商設備封裝： | 408-TBGA（37.5x37.5） |
| 包裝： | 托盤 |
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MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
11
Electrical and Thermal Characteristics
2.3.1
Layout Practices
Each VCC pin should be provided with a low-impedance path to the board’s power supply. Each ground
pin should likewise be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on chip. The VCC power supply should be bypassed to ground using at least four
0.1 F by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads
and associated printed circuit traces connecting to chip VCC and ground should be kept to less than half an
inch per capacitor lead. A four-layer board is recommended, employing two inner layers as V
CC and GND
planes.
All output pins on the MPC8260 have fast rise and fall times. Printed circuit (PC) trace interconnection
length should be minimized in order to minimize overdamped conditions and reflections caused by these
fast output switching times. This recommendation particularly applies to the address and data buses.
Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all
device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and
bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be
inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.
Table 5 provides preliminary, estimated power dissipation for various configurations. Note that suitable
thermal management is required for conditions above PD = 3W (when the ambient temperature is 70° C or
greater) to ensure the junction temperature does not exceed the maximum specified value. Also note that
the I/O power should be included when determining whether to use a heat sink.
Table 5. Estimated Power Dissipation for Various Configurations1
1 Test temperature = room temperature (25° C)
Bus
(MHz)
CPM
Multiplier
CPU
Multiplier
CPM
(MHz)
CPU
(MHz)
PINT (W)
2
2 P
INT = IDD x VDD Watts
Vddl
2.4
2.5
2.6
2.7
2.83
3 2.8 Vddl does not apply to HiP3 Rev C silicon.
33.3
4
133.3
2.04
2.14
2.26
2.38
2.50
50.0
2
3
100
150.0
2.21
2.30
2.45
2.59
2.69
66.7
2
2.5
133.3
166.7
2.47
2.62
2.74
2.88
3.02
66.7
2.5
166.7
2.57
2.69
2.83
2.98
3.12
66.7
2
3
133.3
200.0
2.81
2.95
3.12
3.29
3.43
66.7
2.5
3
166.7
200.0
2.88
3.05
3.22
3.38
3.55
50.0
3
4
150
200.0
2.83
3.00
3.14
3.31
3.48
Note:
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