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參數(shù)資料
| 型號： | KXPC823VR81B2T |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU POWERQUICC 81MHZ 256-PBGA |
| 標準包裝： | 2 |
| 系列： | MPC8xx |
| 處理器類型： | 32-位 MPC8xx PowerQUICC |
| 速度： | 81MHz |
| 電壓： | 1.8V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA |
| 供應商設備封裝： | 256-PBGA（23x23） |
| 包裝： | 托盤 |
8
MPC823 Mobile Computing Microprocessor
MOTOROLA
Embedded PowerPC Core
The PowerPC core complies with standard PowerPC architecture. It has a fully static design that
consists of an integer block, hardware multiplier/divider block and load/store block. The core
supports integer operations on a 32-bit internal data path and 32-bit arithmetic hardware. Its
interface to the internal and external buses is 32 bits. The core uses a two-instruction load/store
queue, four-instruction prefetch queue, and a six-instruction history buffer. It performs branch
folding and branch prediction with conditional prefetch, but without conditional execution. With
single bus cycles, the core can operate on 32-bit external operands and with critical-word-rst in
multiple bus cycles. The PowerPC integer block supports 32 x 32-bit xed-point general-purpose
registers and can execute one integer instruction per clock cycle.
The PowerPC core is integrated with the memory management units, an instruction cache, and a
data cache. The memory management units provide 8-entry, fully associative instruction and data
TLBs, with multiple page sizes of 4K (1K protection), 16K, 512K, and 8M. They support 16 virtual
address spaces and 16 protection groups. Special registers are available to support software
tablewalk and update.
The instruction cache is 2K, two-way, set-associative with physical addressing. It allows
single-cycle accesses on hit with no added latency for miss. It is four words per line and supports
burst line ll using an LRU replacement algorithm. The cache can be locked on a line basis for
application critical routines. The data cache is 1K, two-way, set-associative with physical
addressing. It allows single-cycle accesses on hit with one added clock latency for miss. It has four
words per line and supports burst line ll using an LRU replacement algorithm. The cache can be
locked on a line basis for application critical data and can be programmed to support copyback or
writethrough mode via the memory management unit. The cache-inhibit mode can be programmed
per MMU page. The PowerPC core, with its instruction and data caches, can deliver approximately
99MIPS at 75MHz (using Dhrystone 2.1) or 172K Dhrystones, based on the assumption that it is
issuing one instruction per cycle with a cache hit rate of 94%.
Communication Processor Module
The communication processor module contains features that allow the MPC823 microprocessor to
excel in imaging, personal communication, and low-power applications. These features are divided
into three categories:
DSP processing
Communication processing
Twelve serial DMA channels and two independent DMA channels
The MPC823 embedded DSP function allows the communication processor module to execute
imaging algorithms in parallel with the PowerPC core to achieve maximum performance with very
little power. The DSP can execute one 16x16 MAC on every clock cycle. It has preprogrammed
ltering functions like FIR, MOD, DEMOD, IIR, and downloadable imaging functions for JPEG
image compression and decompression. These functions are also used by modem and speech
recognition programs.
The robust communication features of the MPC823 are provided by the communication processor
module. These features include a RISC microcontroller with multiply accumulate hardware, two
serial communication controllers, two serial management controllers, one dedicated serial channel
for the universal serial bus, one inter-integrated circuit port, one serial peripheral interface, an 8K
dual-port RAM, interrupt controller, two time-slot assigners, and four independent baud rate
generators.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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