102A (5) T
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    參數(shù)資料
    型號: KSZ9021RLI
    廠商: Micrel Inc
    文件頁數(shù): 7/58頁
    文件大?。?/td> 0K
    描述: TXRX ETHERNET GB RGMII 64-LQFP
    標準包裝: 160
    類型: 收發(fā)器
    驅動器/接收器數(shù): 8/8
    規(guī)程: 千兆位以太網(wǎng)
    電源電壓: 3.135 V ~ 3.465 V
    安裝類型: 表面貼裝
    封裝/外殼: 64-LQFP 裸露焊盤
    供應商設備封裝: 64-E-LQFP
    包裝: 托盤
    其它名稱: 576-3636
    KSZ9021RLI-ND
    2010 Microchip Technology Inc.
    DS22265A-page 15
    MCP444X/446X
    102A (5)
    TRSCL
    SCL rise time
    100 kHz mode
    1000
    ns
    Cb is specified to be from
    10 to 400 pF (100 pF maxi-
    mum for 3.4 MHz mode)
    400 kHz mode
    20 + 0.1Cb
    300
    ns
    1.7 MHz mode
    20
    80
    ns
    1.7 MHz mode
    20
    160
    ns
    After a Repeated Start con-
    dition or an Acknowledge
    bit
    3.4 MHz mode
    10
    40
    ns
    3.4 MHz mode
    10
    80
    ns
    After a Repeated Start
    condition or an Acknowl-
    edge bit
    102B (5)
    TRSDA
    SDA rise time
    100 kHz mode
    1000
    ns
    Cb is specified to be from
    10 to 400 pF (100 pF max
    for 3.4 MHz mode)
    400 kHz mode
    20 + 0.1Cb
    300
    ns
    1.7 MHz mode
    20
    160
    ns
    3.4 MHz mode
    10
    80
    ns
    103A (5)
    TFSCL
    SCL fall time
    100 kHz mode
    300
    ns
    Cb is specified to be from
    10 to 400 pF (100 pF max
    for 3.4 MHz mode)
    400 kHz mode
    20 + 0.1Cb
    300
    ns
    1.7 MHz mode
    20
    80
    ns
    3.4 MHz mode
    10
    40
    ns
    103B (5)
    TFSDA
    SDA fall time
    100 kHz mode
    300
    ns
    Cb is specified to be from
    10 to 400 pF (100 pF max
    for 3.4 MHz mode)
    400 kHz mode
    20 + 0.1Cb (4)
    300
    ns
    1.7 MHz mode
    20
    160
    ns
    3.4 MHz mode
    10
    80
    ns
    106
    THD:DAT Data input hold
    time
    100 kHz mode
    0
    ns
    1.8V-5.5V, Note 6
    400 kHz mode
    0
    ns
    2.7V-5.5V, Note 6
    1.7 MHz mode
    0
    ns
    4.5V-5.5V, Note 6
    3.4 MHz mode
    0
    ns
    4.5V-5.5V, Note 6
    TABLE 1-3:
    I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
    I2C AC Characteristics
    Standard Operating Conditions (unless otherwise specified)
    Operating Temperature
    –40
    °C ≤ TA ≤ +125°C (Extended)
    Operating Voltage VDD range is described in AC/DC characteristics
    Param.
    No.
    Sym
    Characteristic
    Min
    Max
    Units
    Conditions
    Note 1:
    As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
    (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
    2:
    A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
    requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not
    stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
    it must output the next data bit to the SDA line
    TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before
    the SCL line is released.
    3:
    The MCP44X1/MCP44X2 device must provide a data hold time to bridge the undefined part between VIH
    and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but
    must be tested in order to ensure that the output data will meet the setup and hold specifications for the
    receiving device.
    4:
    Use Cb in pF for the calculations.
    5:
    Not Tested.
    6:
    A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
    not unintentionally create a Start or Stop condition.
    7:
    Ensured by the TAA 3.4 MHz specification test.
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